arm64: remove ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
With the removal of secmon from coreboot there are no power down operations required. As such remove the A57 power down support. Change-Id: I8eebb0ecd87b5e8bb3eaac335d652689d7f57796 Signed-off-by: Aaron Durbin <adurbin@chromium.org> Reviewed-on: http://review.coreboot.org/11898 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) Reviewed-by: Alexandru Gagniuc <mr.nuke.me@gmail.com> Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
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@ -14,14 +14,8 @@
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*/
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void arm64_cpu_early_setup(void);
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void cortex_a57_cpu_power_down(int l2_flush);
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void __attribute__((weak)) arm64_cpu_early_setup(void)
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{
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/* Default empty implementation */
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}
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void __attribute__((weak)) cortex_a57_cpu_power_down(int l2_flush)
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{
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/* Default empty implementation */
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}
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@ -17,8 +17,3 @@ config ARCH_ARM64_CPU_CORTEX_A57
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bool
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default n
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depends on ARCH_ARM64
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config ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
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bool
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default n
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depends on ARCH_ARM64 && ARCH_ARM64_CPU_CORTEX_A57
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@ -14,7 +14,6 @@
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*/
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#include <arch/asm.h>
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#include <arch/cache_helpers.h>
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#include <cpu/cortex_a57.h>
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ENTRY(arm64_cpu_early_setup)
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@ -24,97 +23,3 @@ ENTRY(arm64_cpu_early_setup)
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isb
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ret
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ENDPROC(arm64_cpu_early_setup)
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/*
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* CPU power down sequence as per A57/A53/A72 TRM
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*
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* x0 - L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported
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*
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*/
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#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT)
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ENTRY(cortex_a57_cpu_power_down)
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/* Store L2 cache flush request */
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mov x13, x0
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/* 1. Stop allocations to our data cache */
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mrs x0, sctlr_el1
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bic x0, x0, #1 << 2 // clear SCTLR.C
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msr sctlr_el1, x0
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isb
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mrs x0, sctlr_el3
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bic x0, x0, #1 << 2 // clear SCTLR.C
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msr sctlr_el3, x0
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isb
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mrs x0, midr_el1
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ubfx x0, x0, #4, #12
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cmp x0, #CORTEX_A53_PN
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b.eq a53
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/* 2. Disable L2 prefetch */
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mrs x0, CPUECTLR_EL1 // CPUECTLR_EL1
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/* CPUECTLR[38], disable table walk descriptor access L2 prefetch */
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orr x0, x0, #1 << 38
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/*
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* CPUECTLR[36:35] L2 instruction fetch prefetch distance
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* 0 => disable instruction prefetch
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*/
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bic x0, x0, #3 << 35
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/*
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* CPUECTLR[33:32] L2 load/store prefetch distance
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* 0 => disable instruction prefetch
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*/
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bic x0, x0, #3 << 32
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msr CPUECTLR_EL1, x0
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/* 3. ISB to ensure ectlr write is complete */
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isb
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/* 4. DSB to ensure prior prefetches are complete */
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dsb sy
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a53:
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/* 5. Clean and invalidate L1 and L2 if X13 == 1 */
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mov x0, #DCCISW
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cmp x13, #1
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bne 1f
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bl flush_dcache_all
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b 2f
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1:
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bl flush_dcache_louis
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2:
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/* 6. Leave coherency, clear SMPEN */
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mrs x0, CPUECTLR_EL1
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bic x0, x0, #(1 << SMPEN_SHIFT)
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msr CPUECTLR_EL1, x0
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/* 7. Set the DBGOSDLR.DLK, Double lock control bit */
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mrs x0, osdlr_el1
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orr x0, x0, #OSDLR_DBL_LOCK_BIT
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msr osdlr_el1, x0
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/*
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* 9. Execute an ISB instruction to ensure that all of the
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* System register changes from the previous steps have
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* been committed.
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*/
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isb
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/*
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* 10. Execute a DSB instruction to ensure that all
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* instruction cache, TLB, and branch predictor
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* maintenance operations issued by any processor in the
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* multiprocessor before the SMPEN bit was cleared have
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* completed.
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*/
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dsb sy
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/* 11. wfi */
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3: wfi
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/* we never return here */
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b 3b
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ENDPROC(cortex_a57_cpu_power_down)
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#endif
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@ -183,18 +183,4 @@ void arm64_cpu_startup_resume(void);
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*/
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void arm64_arch_timer_init(void);
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/*
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* The cortex_a57_cpu_power_down sequence as per A57/A53/A72 TRM.
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* L2 flush by HW(0) or SW(1), if system/HW driven L2 flush is supported.
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*/
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#define NO_L2_FLUSH 0
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#define L2_FLUSH_HW 0
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#define L2_FLUSH_SW 1
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#if IS_ENABLED(CONFIG_ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT)
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void cortex_a57_cpu_power_down(int l2_flush);
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#else
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static inline void cortex_a57_cpu_power_down(int l2_flush) {}
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#endif
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#endif /* __ARCH_CPU_H__ */
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@ -6,7 +6,6 @@ config SOC_NVIDIA_TEGRA210
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select ARCH_ROMSTAGE_ARMV4
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select ARCH_RAMSTAGE_ARMV8_64
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select ARCH_ARM64_CPU_CORTEX_A57
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select ARCH_ARM64_CORTEX_A57_POWER_DOWN_SUPPORT
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select BOOTBLOCK_CONSOLE
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select GIC
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select HAVE_MONOTONIC_TIMER
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