GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectively 

1. SKU1 for eMMC
2. SKU2 for SSD

BUG=b:140008849, b:140573677
TEST=Verify SSD is disabled when SKU ID = 2/4/21/22

Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com>
Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f
Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Marco Chen <marcochen@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peichao Wang 2019-09-02 10:10:57 +08:00 committed by Martin Roth
parent 80d0b01b38
commit 0328a723b8
3 changed files with 204 additions and 24 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

1
src/mainboard/google/hatch/variants/akemi/Makefile.inc
View File

@ -21,3 +21,4 @@ SPD_SOURCES += 16G_2666 # 0b101
bootblock-y += gpio.c bootblock-y += gpio.c
ramstage-y += gpio.c ramstage-y += gpio.c
ramstage-y += variant.c

177
src/mainboard/google/hatch/variants/akemi/gpio.c
View File

@ -19,6 +19,148 @@
#include <commonlib/helpers.h> #include <commonlib/helpers.h>
#include <console/console.h> #include <console/console.h>
static const struct pad_config ssd_sku_gpio_table[] = {
/* A0 : NC */
PAD_NC(GPP_A0, NONE),
/* A6 : NC */
PAD_NC(GPP_A6, NONE),
/* A8 : NC */
PAD_NC(GPP_A8, NONE),
/* A10 : NC */
PAD_NC(GPP_A10, NONE),
/* A11 : NC */
PAD_NC(GPP_A11, NONE),
/* A12 : NC */
PAD_NC(GPP_A12, NONE),
/* A18 : NC */
PAD_NC(GPP_A18, NONE),
/* A19 : NC */
PAD_NC(GPP_A19, NONE),
/* A22 : NC */
PAD_NC(GPP_A22, NONE),
/* A23 : NC */
PAD_NC(GPP_A23, NONE),
/* B20 : NC */
PAD_NC(GPP_B20, NONE),
/* B21 : NC */
PAD_NC(GPP_B21, NONE),
/* B22 : NC */
PAD_NC(GPP_B22, NONE),
/* C11 : NC */
PAD_NC(GPP_C11, NONE),
/* C15 : NC */
PAD_NC(GPP_C15, NONE),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */
PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
/* F11 : NC */
PAD_NC(GPP_F11, NONE),
/* F12 : NC */
PAD_NC(GPP_F12, NONE),
/* F13 : NC */
PAD_NC(GPP_F13, NONE),
/* F14 : NC */
PAD_NC(GPP_F14, NONE),
/* F15 : NC */
PAD_NC(GPP_F15, NONE),
/* F16 : NC */
PAD_NC(GPP_F16, NONE),
/* F17 : NC */
PAD_NC(GPP_F17, NONE),
/* F18 : NC */
PAD_NC(GPP_F18, NONE),
/* F19 : NC */
PAD_NC(GPP_F19, NONE),
/* F20 : NC */
PAD_NC(GPP_F20, NONE),
/* F21 : NC */
PAD_NC(GPP_F21, NONE),
/* F22 : NC */
PAD_NC(GPP_F22, NONE),
/* H6 : NC */
PAD_NC(GPP_H6, NONE),
/* H7 : NC */
PAD_NC(GPP_H7, NONE),
/* H19 : MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
/* H22 : MEM_STRAP_1 */
PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
};
static const struct pad_config emmc_sku_gpio_table[] = {
/* A0 : NC */
PAD_NC(GPP_A0, NONE),
/* A6 : NC */
PAD_NC(GPP_A6, NONE),
/* A8 : NC */
PAD_NC(GPP_A8, NONE),
/* A10 : NC */
PAD_NC(GPP_A10, NONE),
/* A11 : NC */
PAD_NC(GPP_A11, NONE),
/* A12 : NC */
PAD_NC(GPP_A12, NONE),
/* A18 : NC */
PAD_NC(GPP_A18, NONE),
/* A19 : NC */
PAD_NC(GPP_A19, NONE),
/* A22 : NC */
PAD_NC(GPP_A22, NONE),
/* A23 : NC */
PAD_NC(GPP_A23, NONE),
/* B20 : NC */
PAD_NC(GPP_B20, NONE),
/* B21 : NC */
PAD_NC(GPP_B21, NONE),
/* B22 : NC */
PAD_NC(GPP_B22, NONE),
/* C11 : NC */
PAD_NC(GPP_C11, NONE),
/* C15 : NC */
PAD_NC(GPP_C15, NONE),
/* F1 : NC */
PAD_NC(GPP_F1, NONE),
/* F3 : MEM_STRAP_3 */
PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
/* F10 : MEM_STRAP_2 */
PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
/* F11 : EMMC_CMD ==> EMMC_CMD */
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* F20 : EMMC_RCLK ==> EMMC_RCLK */
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* F21 : EMMC_CLK ==> EMMC_CLK */
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* F22 : EMMC_RESET# ==> EMMC_RST_L */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
/* H6 : NC */
PAD_NC(GPP_H6, NONE),
/* H7 : NC */
PAD_NC(GPP_H7, NONE),
/* H19 : MEM_STRAP_0 */
PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
/* H22 : MEM_STRAP_1 */
PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
};
static const struct pad_config gpio_table[] = { static const struct pad_config gpio_table[] = {
/* A0 : NC */ /* A0 : NC */
PAD_NC(GPP_A0, NONE), PAD_NC(GPP_A0, NONE),
@ -92,6 +234,17 @@ static const struct pad_config gpio_table[] = {
const struct pad_config *override_gpio_table(size_t *num) const struct pad_config *override_gpio_table(size_t *num)
{ {
uint32_t sku_id = get_board_sku();
/* For SSD SKU */
if (sku_id == 2) {
*num = ARRAY_SIZE(ssd_sku_gpio_table);
return ssd_sku_gpio_table;
}
/* For eMMC SKU */
if (sku_id == 1) {
*num = ARRAY_SIZE(emmc_sku_gpio_table);
return emmc_sku_gpio_table;
}
*num = ARRAY_SIZE(gpio_table); *num = ARRAY_SIZE(gpio_table);
return gpio_table; return gpio_table;
} }
@ -128,30 +281,6 @@ static const struct pad_config early_gpio_table[] = {
PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1), PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
/* F2 : MEM_CH_SEL */ /* F2 : MEM_CH_SEL */
PAD_CFG_GPI(GPP_F2, NONE, PLTRST), PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
/* F11 : EMMC_CMD ==> EMMC_CMD */
PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
/* F20 : EMMC_RCLK ==> EMMC_RCLK */
PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
/* F21 : EMMC_CLK ==> EMMC_CLK */
PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
/* F22 : EMMC_RESET# ==> EMMC_RST_L */
PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
}; };
const struct pad_config *variant_early_gpio_table(size_t *num) const struct pad_config *variant_early_gpio_table(size_t *num)

50
src/mainboard/google/hatch/variants/akemi/variant.c Normal file
View File

@ -0,0 +1,50 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2019 Google LLC
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <baseboard/variants.h>
#include <chip.h>
#include <soc/pci_devs.h>
#include <ec/google/chromeec/ec.h>
void variant_devtree_update(void)
{
uint32_t sku_id;
struct device *emmc_host;
struct device *ssd_host;
config_t *cfg = config_of_path(SA_DEVFN_ROOT);
emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC);
ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);
/* SKU ID 2 doesn't have a eMMC device, hence disable it. */
sku_id = get_board_sku();
if (sku_id == 2) {
if (emmc_host == NULL)
return;
emmc_host->enabled = 0;
cfg->ScsEmmcHs400Enabled = 0;
}
/* SKU ID 1 doesn't have a SSD device, hence disable it. */
if (sku_id == 1) {
if (ssd_host == NULL)
return;
ssd_host->enabled = 0;
cfg->SataSalpSupport = 0;
cfg->SataMode = 0;
cfg->SataPortsEnable[1] = 0;
cfg->SataPortsDevSlp[1] = 0;
cfg->satapwroptimize = 0;
}
}