mb/google/hatch: Distinguish SKU1 and 2 for eMMC and SSD respectively
1. SKU1 for eMMC 2. SKU2 for SSD BUG=b:140008849, b:140573677 TEST=Verify SSD is disabled when SKU ID = 2/4/21/22 Signed-off-by: Peichao Wang <peichao.wang@bitland.corp-partner.google.com> Change-Id: I827e6f1420801d43e0eb4708b8b8ad1692ef7e9f Reviewed-on: https://review.coreboot.org/c/coreboot/+/35204 Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Marco Chen <marcochen@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Peichao Wang
Martin Roth
parent
80d0b01b38
commit
0328a723b8
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@ -21,3 +21,4 @@ SPD_SOURCES += 16G_2666 # 0b101
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bootblock-y += gpio.c
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ramstage-y += gpio.c
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ramstage-y += variant.c
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@ -19,6 +19,148 @@
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#include <commonlib/helpers.h>
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#include <console/console.h>
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static const struct pad_config ssd_sku_gpio_table[] = {
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/* A0 : NC */
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PAD_NC(GPP_A0, NONE),
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/* A6 : NC */
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PAD_NC(GPP_A6, NONE),
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/* A8 : NC */
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PAD_NC(GPP_A8, NONE),
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/* A10 : NC */
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PAD_NC(GPP_A10, NONE),
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/* A11 : NC */
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PAD_NC(GPP_A11, NONE),
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/* A12 : NC */
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PAD_NC(GPP_A12, NONE),
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/* A18 : NC */
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PAD_NC(GPP_A18, NONE),
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/* A19 : NC */
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PAD_NC(GPP_A19, NONE),
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/* A22 : NC */
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PAD_NC(GPP_A22, NONE),
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/* A23 : NC */
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PAD_NC(GPP_A23, NONE),
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/* B20 : NC */
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PAD_NC(GPP_B20, NONE),
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/* B21 : NC */
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PAD_NC(GPP_B21, NONE),
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/* B22 : NC */
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PAD_NC(GPP_B22, NONE),
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/* C11 : NC */
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PAD_NC(GPP_C11, NONE),
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/* C15 : NC */
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PAD_NC(GPP_C15, NONE),
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/* F1 : NC */
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PAD_NC(GPP_F1, NONE),
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/* F3 : MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
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/* F10 : MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
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/* F11 : NC */
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PAD_NC(GPP_F11, NONE),
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/* F12 : NC */
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PAD_NC(GPP_F12, NONE),
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/* F13 : NC */
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PAD_NC(GPP_F13, NONE),
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/* F14 : NC */
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PAD_NC(GPP_F14, NONE),
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/* F15 : NC */
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PAD_NC(GPP_F15, NONE),
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/* F16 : NC */
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PAD_NC(GPP_F16, NONE),
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/* F17 : NC */
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PAD_NC(GPP_F17, NONE),
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/* F18 : NC */
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PAD_NC(GPP_F18, NONE),
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/* F19 : NC */
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PAD_NC(GPP_F19, NONE),
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/* F20 : NC */
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PAD_NC(GPP_F20, NONE),
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/* F21 : NC */
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PAD_NC(GPP_F21, NONE),
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/* F22 : NC */
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PAD_NC(GPP_F22, NONE),
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/* H6 : NC */
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PAD_NC(GPP_H6, NONE),
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/* H7 : NC */
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PAD_NC(GPP_H7, NONE),
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/* H19 : MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
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/* H22 : MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
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};
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static const struct pad_config emmc_sku_gpio_table[] = {
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/* A0 : NC */
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PAD_NC(GPP_A0, NONE),
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/* A6 : NC */
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PAD_NC(GPP_A6, NONE),
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/* A8 : NC */
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PAD_NC(GPP_A8, NONE),
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/* A10 : NC */
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PAD_NC(GPP_A10, NONE),
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/* A11 : NC */
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PAD_NC(GPP_A11, NONE),
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/* A12 : NC */
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PAD_NC(GPP_A12, NONE),
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/* A18 : NC */
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PAD_NC(GPP_A18, NONE),
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/* A19 : NC */
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PAD_NC(GPP_A19, NONE),
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/* A22 : NC */
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PAD_NC(GPP_A22, NONE),
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/* A23 : NC */
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PAD_NC(GPP_A23, NONE),
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/* B20 : NC */
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PAD_NC(GPP_B20, NONE),
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/* B21 : NC */
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PAD_NC(GPP_B21, NONE),
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/* B22 : NC */
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PAD_NC(GPP_B22, NONE),
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/* C11 : NC */
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PAD_NC(GPP_C11, NONE),
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/* C15 : NC */
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PAD_NC(GPP_C15, NONE),
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/* F1 : NC */
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PAD_NC(GPP_F1, NONE),
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/* F3 : MEM_STRAP_3 */
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PAD_CFG_GPI(GPP_F3, NONE, PLTRST),
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/* F10 : MEM_STRAP_2 */
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PAD_CFG_GPI(GPP_F10, NONE, PLTRST),
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/* F11 : EMMC_CMD ==> EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_RCLK ==> EMMC_RCLK */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_CLK ==> EMMC_CLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_RESET# ==> EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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/* H6 : NC */
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PAD_NC(GPP_H6, NONE),
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/* H7 : NC */
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PAD_NC(GPP_H7, NONE),
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/* H19 : MEM_STRAP_0 */
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PAD_CFG_GPI(GPP_H19, NONE, PLTRST),
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/* H22 : MEM_STRAP_1 */
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PAD_CFG_GPI(GPP_H22, NONE, PLTRST),
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};
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static const struct pad_config gpio_table[] = {
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/* A0 : NC */
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PAD_NC(GPP_A0, NONE),
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@ -92,6 +234,17 @@ static const struct pad_config gpio_table[] = {
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const struct pad_config *override_gpio_table(size_t *num)
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{
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uint32_t sku_id = get_board_sku();
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/* For SSD SKU */
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if (sku_id == 2) {
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*num = ARRAY_SIZE(ssd_sku_gpio_table);
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return ssd_sku_gpio_table;
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}
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/* For eMMC SKU */
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if (sku_id == 1) {
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*num = ARRAY_SIZE(emmc_sku_gpio_table);
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return emmc_sku_gpio_table;
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}
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*num = ARRAY_SIZE(gpio_table);
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return gpio_table;
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}
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@ -128,30 +281,6 @@ static const struct pad_config early_gpio_table[] = {
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PAD_CFG_NF(GPP_E5, NONE, PLTRST, NF1),
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/* F2 : MEM_CH_SEL */
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PAD_CFG_GPI(GPP_F2, NONE, PLTRST),
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/* F11 : EMMC_CMD ==> EMMC_CMD */
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PAD_CFG_NF(GPP_F11, NONE, DEEP, NF1),
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/* F12 : EMMC_DATA0 ==> EMMC_DAT0 */
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PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
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/* F13 : EMMC_DATA1 ==> EMMC_DAT1 */
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PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
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/* F14 : EMMC_DATA2 ==> EMMC_DAT2 */
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PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
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/* F15 : EMMC_DATA3 ==> EMMC_DAT3 */
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PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
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/* F16 : EMMC_DATA4 ==> EMMC_DAT4 */
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PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
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/* F17 : EMMC_DATA5 ==> EMMC_DAT5 */
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PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
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/* F18 : EMMC_DATA6 ==> EMMC_DAT6 */
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PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
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/* F19 : EMMC_DATA7 ==> EMMC_DAT7 */
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PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
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/* F20 : EMMC_RCLK ==> EMMC_RCLK */
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PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
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/* F21 : EMMC_CLK ==> EMMC_CLK */
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PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
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/* F22 : EMMC_RESET# ==> EMMC_RST_L */
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PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
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};
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const struct pad_config *variant_early_gpio_table(size_t *num)
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@ -0,0 +1,50 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2019 Google LLC
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <baseboard/variants.h>
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#include <chip.h>
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#include <soc/pci_devs.h>
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#include <ec/google/chromeec/ec.h>
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void variant_devtree_update(void)
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{
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uint32_t sku_id;
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struct device *emmc_host;
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struct device *ssd_host;
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config_t *cfg = config_of_path(SA_DEVFN_ROOT);
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emmc_host = pcidev_path_on_root(PCH_DEVFN_EMMC);
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ssd_host = pcidev_path_on_root(PCH_DEVFN_SATA);
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/* SKU ID 2 doesn't have a eMMC device, hence disable it. */
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sku_id = get_board_sku();
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if (sku_id == 2) {
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if (emmc_host == NULL)
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return;
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emmc_host->enabled = 0;
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cfg->ScsEmmcHs400Enabled = 0;
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}
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/* SKU ID 1 doesn't have a SSD device, hence disable it. */
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if (sku_id == 1) {
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if (ssd_host == NULL)
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return;
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ssd_host->enabled = 0;
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cfg->SataSalpSupport = 0;
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cfg->SataMode = 0;
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cfg->SataPortsEnable[1] = 0;
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cfg->SataPortsDevSlp[1] = 0;
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cfg->satapwroptimize = 0;
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}
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}
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