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Revert "soc/amd/stoneyridge/gpio: Configure debounce for irq gpios" 

This reverts commit b82afce18a.

Reason for revert: This causes depthcharge to not boot due to TPM timeout errors. Because there is no wait after setting the debounce register, we lose data because the read-modify-write loses the interrupt status bit.

e.g., GPIO 5 sets debounce, without a wait. Then GPIO 9 has it's debounce set. Because the interrupt controller is masking the interrupt enable status bit, the read-modify-write for GPIO9 loses the interrupt enable status bit and it never gets set again. This causes the interrupt to never latch.

We should possibly make depthcharge set the interrupt enable status bit for latched GPIOs.

Change-Id: Idd7259b14b24c441529d64e173be9faec03f4fc8
Signed-off-by: Raul E Rangel <rrangel@chromium.org>
Signed-off-by: Martin Roth <martinroth@google.com>
Reviewed-on: https://review.coreboot.org/c/30981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Daniel Kurtz <djkurtz@google.com>
This commit is contained in:
Raul Rangel 2019-01-17 21:39:19 +00:00 committed by Patrick Georgi
parent da02719462
commit 034e5e6fa5
2 changed files with 1 additions and 36 deletions
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35
src/soc/amd/stoneyridge/gpio.c
View File

@ -219,41 +219,12 @@ uint16_t gpio_acpi_pin(gpio_t gpio)
return gpio;
}
/*
* Returns the debounce type corresponding to a given interrupt type.
*
* This matches what the linux kernel will set during gpio configuration:
*
* Interrupt Debounce
* Edge Remove Glitch
* Level High Preserve Low Glitch
* Level Low Preserve High Glitch
*/
static uint32_t gpio_irq_debounce(uint32_t flag)
{
uint32_t trigger;
trigger = flag & FLAGS_TRIGGER_MASK;
switch (trigger) {
case GPIO_TRIGGER_LEVEL_LOW:
return GPIO_IN_PRESERVE_HIGH_GLITCH;
case GPIO_TRIGGER_LEVEL_HIGH:
return GPIO_IN_PRESERVE_LOW_GLITCH;
case GPIO_TRIGGER_EDGE_LOW:
return GPIO_IN_REMOVE_GLITCH;
case GPIO_TRIGGER_EDGE_HIGH:
return GPIO_IN_REMOVE_GLITCH;
default:
return GPIO_IN_NO_DEBOUNCE;
}
}
void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
{
uint8_t *mux_ptr;
uint32_t *gpio_ptr;
uint32_t control, control_flags, edge_level, direction;
uint32_t mask, bit_edge, bit_level, debounce;
uint32_t mask, bit_edge, bit_level;
uint8_t mux, index, gpio;
int gevent_num;
@ -302,10 +273,6 @@ void sb_program_gpios(const struct soc_amd_gpio *gpio_list_ptr, size_t size)
case GPIO_SCI_FLAG:
mem_read_write32(gpio_ptr, control,
INT_SCI_SMI_MASK);
/* Always set debounce type for SCI gpio */
debounce = gpio_irq_debounce(control_flags);
mem_read_write32(gpio_ptr, debounce,
GPIO_DEBOUNCE_MASK);
get_sci_config_bits(control_flags, &bit_edge,
&bit_level);
edge_level |= bit_edge << gevent_num;

2
src/soc/amd/stoneyridge/include/soc/gpio.h
View File

@ -450,11 +450,9 @@ enum {
#define INT_SCI_SMI_MASK 0x00f40000
#define IN_GLITCH_SHIFT 5
#define DEBOUNCE_NONE 0
#define GLITCH_LOW 1
#define GLITCH_HIGH 2
#define GLITCH_NONE 3
#define GPIO_IN_NO_DEBOUNCE (DEBOUNCE_NONE << IN_GLITCH_SHIFT)
#define GPIO_IN_PRESERVE_LOW_GLITCH (GLITCH_LOW << IN_GLITCH_SHIFT)
#define GPIO_IN_PRESERVE_HIGH_GLITCH (GLITCH_HIGH << IN_GLITCH_SHIFT)
#define GPIO_IN_REMOVE_GLITCH (GLITCH_NONE << IN_GLITCH_SHIFT)