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mb/intel/saddlebrook: Fix 2nd DIMM slot 

Assumed broken during review and rebase. The
SPD at address 0x52 will appear at index 1.

Change-Id: I213853d2b981294554d8d1b254da476905a41c13
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/31630
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: PraveenX Hodagatta Pranesh <praveenx.hodagatta.pranesh@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2019-02-27 08:15:01 +02:00
parent 7ba14406c3
commit 035876c4dd
1 changed files with 1 additions and 1 deletions
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2
src/mainboard/intel/saddlebrook/romstage.c
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@ -56,7 +56,7 @@ void mainboard_memory_init_params(
printk(BIOS_SPEW, "spd block length: 0x%08x\n", blk.len);
memory_params->MemorySpdPtr00 = (UINT32) blk.spd_array[0];
memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[2];
memory_params->MemorySpdPtr10 = (UINT32) blk.spd_array[1];
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_0_0\n",
memory_params->MemorySpdPtr00);
printk(BIOS_SPEW, "0x%08x: SpdDataBuffer_1_0\n",