soc/intel: Make use of PMC low power program from common block

List of changes:
1. Select PMC_LOW_POWER_MODE_PROGRAM from applicable SoC directory
2. Remove redundant PMC programming from SoC and refer to common
code block
3. Remove unused 'reg8' and 'reg32' variable as applicable from SoC
function.

Change-Id: I18894c49cfc6e88675b5fb71bca0412e5639fb4b
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/45796
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/Kconfig

@@ -96,6 +96,7 @@ config CPU_SPECIFIC_OPTIONS
 	select PLATFORM_USES_FSP2_0
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select PMC_LOW_POWER_MODE_PROGRAM
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK

src/soc/intel/cannonlake/finalize.c

@@ -9,6 +9,7 @@
 #include <device/pci.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
 #include <spi-generic.h>
@@ -44,7 +45,6 @@ static void pch_finalize(void)
 	uint32_t reg32;
 	uint8_t *pmcbase;
 	config_t *config;
-	uint8_t reg8;
 
 	tco_lockdown();
 
@@ -70,17 +70,12 @@ static void pch_finalize(void)
 	 */
 	config = config_of_soc();
 	pmcbase = pmc_mmio_regs();
-	if (config->PmTimerDisabled) {
-		reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
-		reg8 |= (1 << 1);
-		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
-	}
+	if (config->PmTimerDisabled)
+		pmc_disable_acpi_timer();
 
 	if (config->s0ix_enable) {
 		/* Disable XTAL shutdown qualification for low power idle. */
-		reg32 = read32(pmcbase + CPPMVRIC);
-		reg32 |= XTALSDQDIS;
-		write32(pmcbase + CPPMVRIC, reg32);
+		pmc_ignore_xtal_shutdown();
 
 		if (config->cppmvric2_adsposcdis) {
 			/* Enable Audio DSP OSC qualification for S0ix */

src/soc/intel/cannonlake/include/soc/pmc.h

@@ -98,6 +98,7 @@
 #define   PCH2CPU_TT_EN			(1 << 26)
 
 #define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define  ACPI_TIM_DIS			(1 << 1)
 #define GPIO_GPE_CFG			0x1920
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))

src/soc/intel/elkhartlake/Kconfig

@@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_PEIM_TO_PEIM_INTERFACE
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select PMC_LOW_POWER_MODE_PROGRAM
 	select CPU_INTEL_COMMON_SMM
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE

src/soc/intel/elkhartlake/finalize.c

@@ -9,6 +9,7 @@
 #include <device/pci.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
 #include <soc/p2sb.h>
@@ -22,10 +23,7 @@
 
 static void pch_finalize(void)
 {
-	uint32_t reg32;
-	uint8_t *pmcbase;
 	config_t *config;
-	uint8_t reg8;
 
 	/* TCO Lock down */
 	tco_lockdown();
@@ -44,19 +42,12 @@ static void pch_finalize(void)
 	 * returns NULL for PCH_DEV_PMC device.
 	 */
 	config = config_of_soc();
-	pmcbase = pmc_mmio_regs();
-	if (config->PmTimerDisabled) {
-		reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
-		reg8 |= (1 << 1);
-		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
-	}
+	if (config->PmTimerDisabled)
+		pmc_disable_acpi_timer();
 
 	/* Disable XTAL shutdown qualification for low power idle. */
-	if (config->s0ix_enable) {
-		reg32 = read32(pmcbase + CPPMVRIC);
-		reg32 |= XTALSDQDIS;
-		write32(pmcbase + CPPMVRIC, reg32);
-	}
+	if (config->s0ix_enable)
+		pmc_ignore_xtal_shutdown();
 
 	pmc_clear_pmcon_sts();
 }

src/soc/intel/elkhartlake/include/soc/pmc.h

@@ -98,6 +98,7 @@
 #define   PCH2CPU_TT_EN			(1 << 26)
 
 #define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define  ACPI_TIM_DIS			(1 << 1)
 #define GPIO_GPE_CFG			0x1920
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))

src/soc/intel/icelake/Kconfig

@@ -30,6 +30,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_PEIM_TO_PEIM_INTERFACE
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select PMC_LOW_POWER_MODE_PROGRAM
 	select CPU_INTEL_COMMON_SMM
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE

src/soc/intel/icelake/finalize.c

@@ -9,6 +9,7 @@
 #include <device/pci.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
 #include <spi-generic.h>
@@ -40,10 +41,7 @@ static void pch_handle_sideband(config_t *config)
 
 static void pch_finalize(void)
 {
-	uint32_t reg32;
-	uint8_t *pmcbase;
 	config_t *config;
-	uint8_t reg8;
 
 	/* TCO Lock down */
 	tco_lockdown();
@@ -69,19 +67,12 @@ static void pch_finalize(void)
 	 * returns NULL for PCH_DEV_PMC device.
 	 */
 	config = config_of_soc();
-	pmcbase = pmc_mmio_regs();
-	if (config->PmTimerDisabled) {
-		reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
-		reg8 |= (1 << 1);
-		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
-	}
+	if (config->PmTimerDisabled)
+		pmc_disable_acpi_timer();
 
 	/* Disable XTAL shutdown qualification for low power idle. */
-	if (config->s0ix_enable) {
-		reg32 = read32(pmcbase + CPPMVRIC);
-		reg32 |= XTALSDQDIS;
-		write32(pmcbase + CPPMVRIC, reg32);
-	}
+	if (config->s0ix_enable)
+		pmc_ignore_xtal_shutdown();
 
 	pch_handle_sideband(config);
 

src/soc/intel/icelake/include/soc/pmc.h

@@ -98,6 +98,7 @@
 #define   PCH2CPU_TT_EN			(1 << 26)
 
 #define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define  ACPI_TIM_DIS			(1 << 1)
 #define GPIO_GPE_CFG			0x1920
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))

src/soc/intel/jasperlake/Kconfig

@@ -32,6 +32,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_PEIM_TO_PEIM_INTERFACE
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select PMC_LOW_POWER_MODE_PROGRAM
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK

src/soc/intel/jasperlake/finalize.c

@@ -9,6 +9,7 @@
 #include <device/pci.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
 #include <spi-generic.h>
@@ -40,10 +41,7 @@ static void pch_handle_sideband(config_t *config)
 
 static void pch_finalize(void)
 {
-	uint32_t reg32;
-	uint8_t *pmcbase;
 	config_t *config;
-	uint8_t reg8;
 
 	/* TCO Lock down */
 	tco_lockdown();
@@ -62,19 +60,12 @@ static void pch_finalize(void)
 	 * returns NULL for PCH_DEV_PMC device.
 	 */
 	config = config_of_soc();
-	pmcbase = pmc_mmio_regs();
-	if (config->PmTimerDisabled) {
-		reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
-		reg8 |= (1 << 1);
-		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
-	}
+	if (config->PmTimerDisabled)
+		pmc_disable_acpi_timer();
 
 	/* Disable XTAL shutdown qualification for low power idle. */
-	if (config->s0ix_enable) {
-		reg32 = read32(pmcbase + CPPMVRIC);
-		reg32 |= XTALSDQDIS;
-		write32(pmcbase + CPPMVRIC, reg32);
-	}
+	if (config->s0ix_enable)
+		pmc_ignore_xtal_shutdown();
 
 	pch_handle_sideband(config);
 

src/soc/intel/jasperlake/include/soc/pmc.h

@@ -98,6 +98,7 @@
 #define   PCH2CPU_TT_EN			(1 << 26)
 
 #define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define  ACPI_TIM_DIS			(1 << 1)
 #define GPIO_GPE_CFG			0x1920
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))

src/soc/intel/skylake/Kconfig

@@ -42,6 +42,7 @@ config CPU_SPECIFIC_OPTIONS
 	select REG_SCRIPT
 	select SA_ENABLE_DPR
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select PMC_LOW_POWER_MODE_PROGRAM
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK

src/soc/intel/skylake/finalize.c

@@ -13,6 +13,7 @@
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/p2sb.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
 #include <spi-generic.h>
@@ -44,17 +45,13 @@ static void pch_disable_heci(void)
 
 static void pch_finalize_script(struct device *dev)
 {
-	uint32_t reg32;
-	uint8_t *pmcbase;
 	config_t *config;
-	u8 reg8;
 
 	tco_lockdown();
 
 	/* Display me status before we hide it */
 	intel_me_status();
 
-	pmcbase = pmc_mmio_regs();
 	config = config_of(dev);
 
 	/*
@@ -73,18 +70,12 @@ static void pch_finalize_script(struct device *dev)
 	 * Disabling ACPI PM timer also switches off TCO
 	 */
 
-	if (config->PmTimerDisabled) {
-		reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
-		reg8 |= (1 << 1);
-		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
-	}
+	if (config->PmTimerDisabled)
+		pmc_disable_acpi_timer();
 
 	/* Disable XTAL shutdown qualification for low power idle. */
-	if (config->s0ix_enable) {
-		reg32 = read32(pmcbase + CPPMVRIC);
-		reg32 |= XTALSDQDIS;
-		write32(pmcbase + CPPMVRIC, reg32);
-	}
+	if (config->s0ix_enable)
+		pmc_ignore_xtal_shutdown();
 
 	/* we should disable Heci1 based on the devicetree policy */
 	if (config->HeciEnabled == 0)

src/soc/intel/skylake/include/soc/pmc.h

@@ -78,6 +78,7 @@
 #define PMSYNC_TPR_CFG		0xc4
 #define  PMSYNC_LOCK		(1 << 31)
 #define PCH_PWRM_ACPI_TMR_CTL	0xfc
+#define  ACPI_TIM_DIS		(1 << 1)
 #define GPIO_GPE_CFG		0x120
 #define  GPE0_DWX_MASK		0xf
 #define GPE0_DW_SHIFT(x)	(4*(x))

src/soc/intel/tigerlake/Kconfig

@@ -33,6 +33,7 @@ config CPU_SPECIFIC_OPTIONS
 	select FSP_PEIM_TO_PEIM_INTERFACE
 	select REG_SCRIPT
 	select PMC_GLOBAL_RESET_ENABLE_LOCK
+	select PMC_LOW_POWER_MODE_PROGRAM
 	select SOC_INTEL_COMMON
 	select SOC_INTEL_COMMON_ACPI_WAKE_SOURCE
 	select SOC_INTEL_COMMON_BLOCK

src/soc/intel/tigerlake/finalize.c

@@ -15,6 +15,7 @@
 #include <device/pci.h>
 #include <intelblocks/lpc_lib.h>
 #include <intelblocks/pcr.h>
+#include <intelblocks/pmclib.h>
 #include <intelblocks/tco.h>
 #include <intelblocks/thermal.h>
 #include <spi-generic.h>
@@ -28,10 +29,7 @@
 
 static void pch_finalize(void)
 {
-	uint32_t reg32;
-	uint8_t *pmcbase;
 	config_t *config;
-	uint8_t reg8;
 
 	/* TCO Lock down */
 	tco_lockdown();
@@ -50,19 +48,12 @@ static void pch_finalize(void)
 	 * returns NULL for PCH_DEV_PMC device.
 	 */
 	config = config_of_soc();
-	pmcbase = pmc_mmio_regs();
-	if (config->PmTimerDisabled) {
-		reg8 = read8(pmcbase + PCH_PWRM_ACPI_TMR_CTL);
-		reg8 |= (1 << 1);
-		write8(pmcbase + PCH_PWRM_ACPI_TMR_CTL, reg8);
-	}
+	if (config->PmTimerDisabled)
+		pmc_disable_acpi_timer();
 
 	/* Disable XTAL shutdown qualification for low power idle. */
-	if (config->s0ix_enable) {
-		reg32 = read32(pmcbase + CPPMVRIC);
-		reg32 |= XTALSDQDIS;
-		write32(pmcbase + CPPMVRIC, reg32);
-	}
+	if (config->s0ix_enable)
+		pmc_ignore_xtal_shutdown();
 
 	pmc_clear_pmcon_sts();
 }

src/soc/intel/tigerlake/include/soc/pmc.h

@@ -126,6 +126,7 @@ enum pch_pmc_xtal {
 enum pch_pmc_xtal pmc_get_xtal_freq(void);
 
 #define PCH_PWRM_ACPI_TMR_CTL		0x18FC
+#define  ACPI_TIM_DIS			(1 << 1)
 #define GPIO_GPE_CFG			0x1920
 #define  GPE0_DWX_MASK			0xf
 #define  GPE0_DW_SHIFT(x)		(4*(x))