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src/southbridge: Remove whitespace after sizeof

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Change-Id: Ic3b599d49a4c03ad8035c558b975f31cb91d253b
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16862
Tested-by: build bot (Jenkins)
Reviewed-by: Jonathan Neuschäfer <j.neuschaefer@gmx.net>
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Elyes HAOUAS 2016-10-03 21:54:16 +02:00 committed by Martin Roth
parent c44fb50185
commit 035df005c5
12 changed files with 20 additions and 20 deletions
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2
src/southbridge/amd/cimx/sb700/AmdSbLib.h
View file

@ -18,7 +18,7 @@
typedef signed char *va_list; typedef signed char *va_list;
#ifndef _INTSIZEOF #ifndef _INTSIZEOF
#define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
#endif #endif
// Also support coding convention rules for var arg macros // Also support coding convention rules for var arg macros

2
src/southbridge/amd/cimx/sb800/AmdSbLib.h
View file

@ -22,7 +22,7 @@
typedef signed char *va_list; typedef signed char *va_list;
#ifndef _INTSIZEOF #ifndef _INTSIZEOF
#define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
#endif #endif
// Also support coding convention rules for var arg macros // Also support coding convention rules for var arg macros

2
src/southbridge/amd/cimx/sb900/AmdSbLib.h
View file

@ -22,7 +22,7 @@
typedef signed char *va_list; typedef signed char *va_list;
#ifndef _INTSIZEOF #ifndef _INTSIZEOF
#define _INTSIZEOF (n) ( (sizeof (n) + sizeof (UINTN) - 1) & ~(sizeof (UINTN) - 1) ) #define _INTSIZEOF (n) ( (sizeof(n) + sizeof(UINTN) - 1) & ~(sizeof(UINTN) - 1) )
#endif #endif
// Also support coding convention rules for var arg macros // Also support coding convention rules for var arg macros

4
src/southbridge/intel/bd82x6x/lpc.c
View file

@ -653,7 +653,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev) static void southbridge_inject_dsdt(device_t dev)
{ {
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
void *opregion; void *opregion;
/* Calling northbridge code as gnvs contains opregion address. */ /* Calling northbridge code as gnvs contains opregion address. */
@ -661,7 +661,7 @@ static void southbridge_inject_dsdt(device_t dev)
if (gnvs) { if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs); acpi_create_gnvs(gnvs);

4
src/southbridge/intel/fsp_bd82x6x/lpc.c
View file

@ -588,7 +588,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev) static void southbridge_inject_dsdt(device_t dev)
{ {
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
void *opregion; void *opregion;
/* Calling northbridge code as gnvs contains opregion address. */ /* Calling northbridge code as gnvs contains opregion address. */
@ -597,7 +597,7 @@ static void southbridge_inject_dsdt(device_t dev)
if (gnvs) { if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs); acpi_create_gnvs(gnvs);
/* IGD OpRegion Base Address */ /* IGD OpRegion Base Address */

4
src/southbridge/intel/fsp_i89xx/lpc.c
View file

@ -500,7 +500,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev) static void southbridge_inject_dsdt(device_t dev)
{ {
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
void *opregion; void *opregion;
/* Calling northbridge code as gnvs contains opregion address. */ /* Calling northbridge code as gnvs contains opregion address. */
@ -509,7 +509,7 @@ static void southbridge_inject_dsdt(device_t dev)
if (gnvs) { if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs); acpi_create_gnvs(gnvs);
/* IGD OpRegion Base Address */ /* IGD OpRegion Base Address */

2
src/southbridge/intel/fsp_rangeley/lpc.c
View file

@ -429,7 +429,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev) static void southbridge_inject_dsdt(device_t dev)
{ {
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) { if (gnvs) {
memset(gnvs, 0, sizeof(*gnvs)); memset(gnvs, 0, sizeof(*gnvs));

2
src/southbridge/intel/i82801gx/lpc.c
View file

@ -656,7 +656,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev) static void southbridge_inject_dsdt(device_t dev)
{ {
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) { if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();

4
src/southbridge/intel/i82801ix/lpc.c
View file

@ -538,11 +538,11 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev) static void southbridge_inject_dsdt(device_t dev)
{ {
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) { if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs); acpi_create_gnvs(gnvs);
gnvs->ndid = gfx->ndid; gnvs->ndid = gfx->ndid;

10
src/southbridge/intel/ibexpeak/lpc.c
View file

@ -310,7 +310,7 @@ static void mobile5_pm_init(struct device *dev)
/* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000, /* 2010: */ 0x00188200, 0x14000016, 0xbc4abcb5, 0x00000000,
/* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170 /* 2020: */ 0xf0c9605b, 0x13683040, 0x04c8f16e, 0x09e90170
}; };
for (i = 0; i < sizeof (rcba2010) / sizeof (rcba2010[0]); i++) for (i = 0; i < sizeof(rcba2010) / sizeof(rcba2010[0]); i++)
{ {
RCBA32 (0x2010 + 4 * i) = rcba2010[i]; RCBA32 (0x2010 + 4 * i) = rcba2010[i];
RCBA32 (0x2010 + 4 * i); RCBA32 (0x2010 + 4 * i);
@ -348,7 +348,7 @@ static void mobile5_pm_init(struct device *dev)
/* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000 /* 2270 */ 0x00001c01, 0x16000000, 0x00010107, 0x00160000
}; };
for (i = 0; i < sizeof (rcba2210) / sizeof (rcba2210[0]); i++) for (i = 0; i < sizeof(rcba2210) / sizeof(rcba2210[0]); i++)
{ {
RCBA32 (0x2210 + 4 * i) = rcba2210[i]; RCBA32 (0x2210 + 4 * i) = rcba2210[i];
RCBA32 (0x2210 + 4 * i); RCBA32 (0x2210 + 4 * i);
@ -361,7 +361,7 @@ static void mobile5_pm_init(struct device *dev)
/* 2320: */ 0xcccc0cfc, 0x0fbb0fff /* 2320: */ 0xcccc0cfc, 0x0fbb0fff
}; };
for (i = 0; i < sizeof (rcba2300) / sizeof (rcba2300[0]); i++) for (i = 0; i < sizeof(rcba2300) / sizeof(rcba2300[0]); i++)
{ {
RCBA32 (0x2300 + 4 * i) = rcba2300[i]; RCBA32 (0x2300 + 4 * i) = rcba2300[i];
RCBA32 (0x2300 + 4 * i); RCBA32 (0x2300 + 4 * i);
@ -619,7 +619,7 @@ static void set_subsystem(device_t dev, unsigned vendor, unsigned device)
static void southbridge_inject_dsdt(device_t dev) static void southbridge_inject_dsdt(device_t dev)
{ {
global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); global_nvs_t *gnvs = cbmem_add (CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
void *opregion; void *opregion;
/* Calling northbridge code as gnvs contains opregion address. */ /* Calling northbridge code as gnvs contains opregion address. */
@ -627,7 +627,7 @@ static void southbridge_inject_dsdt(device_t dev)
if (gnvs) { if (gnvs) {
const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info(); const struct i915_gpu_controller_info *gfx = intel_gma_get_controller_info();
memset(gnvs, 0, sizeof (*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
acpi_create_gnvs(gnvs); acpi_create_gnvs(gnvs);

2
src/southbridge/intel/lynxpoint/acpi.c
View file

@ -56,7 +56,7 @@ void acpi_create_intel_hpet(acpi_hpet_t * hpet)
static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs) static void acpi_create_serialio_ssdt_entry(int id, global_nvs_t *gnvs)
{ {
char sio_name[5] = {}; char sio_name[5] = {};
snprintf(sio_name, sizeof (sio_name), "S%1uEN", id); snprintf(sio_name, sizeof(sio_name), "S%1uEN", id);
acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0); acpigen_write_name_byte(sio_name, gnvs->s0b[id] ? 1 : 0);
} }

2
src/southbridge/intel/lynxpoint/lpc.c
View file

@ -748,7 +748,7 @@ static void southbridge_inject_dsdt(device_t dev)
gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS); gnvs = cbmem_find(CBMEM_ID_ACPI_GNVS);
if (!gnvs) { if (!gnvs) {
gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof (*gnvs)); gnvs = cbmem_add(CBMEM_ID_ACPI_GNVS, sizeof(*gnvs));
if (gnvs) if (gnvs)
memset(gnvs, 0, sizeof(*gnvs)); memset(gnvs, 0, sizeof(*gnvs));
} }