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sb/amd/pi/hudson/early_init: fix setting SPI_USE_SPI100 in SPI100_ENABLE 

Use a read modify write sequence when setting the SPI_USE_SPI100 bit in
the SPI100_ENABLE register. This avoids clearing other bits in the
register which might cause instabilities. Haven't checked the reference
code, but the register descriptions suggested that the register in
Mullins behaves similar to the one in Stoneyridge. Right now this code
is unused, but it's probably still a good idea to fix it.

TEST=Booting Debian 11 with kernel 5.10 on apu2 still works when adding
a call to hudson_set_spi100 with this patch applied.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ifbd960a9509542b28f03326a3066995540260bef
Tested-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59934
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-by: Michał Żygowski <michal.zygowski@3mdeb.com>
This commit is contained in:
Felix Held 2021-12-07 00:38:29 +01:00
parent 688f09f97a
commit 0365fc8186
1 changed files with 2 additions and 1 deletions
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3
src/southbridge/amd/pi/hudson/early_setup.c
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@ -215,7 +215,8 @@ void hudson_set_spi100(u16 norm, u16 fast, u16 alt, u16 tpm)
(fast << SPI_FAST_SPEED_NEW_SH) | (fast << SPI_FAST_SPEED_NEW_SH) |
(alt << SPI_ALT_SPEED_NEW_SH) | (alt << SPI_ALT_SPEED_NEW_SH) |
(tpm << SPI_TPM_SPEED_NEW_SH)); (tpm << SPI_TPM_SPEED_NEW_SH));
write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100); write16((void *)(base + SPI100_ENABLE), SPI_USE_SPI100 |
read16((void *)(base + SPI100_ENABLE)));
} }
void hudson_disable_4dw_burst(void) void hudson_disable_4dw_burst(void)