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soc/intel/alderlake_n: Enable FIVR VCCST ICCMax Control 

Enable the VCCST ICCMax Control for the ADL-N display flicker issue.
Please refer the Doc with ID 742988 for more details.

BUG=b:248249033
TEST=Verified that the display flicker issue is fixed.

Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I10709ee8653563b397e8408e8e24ef8e656b02e5
Reviewed-on: https://review.coreboot.org/c/coreboot/+/68252
Reviewed-by: Reka Norman <rekanorman@chromium.org>
Reviewed-by: Baieswara Reddy Sagili <baieswara.reddy.sagili@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kangheui Won <khwon@chromium.org>
This commit is contained in:
V Sowmya 2022-10-10 12:46:18 +05:30 committed by Martin L Roth
parent 901566597e
commit 036b16b884
1 changed files with 9 additions and 0 deletions
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9
src/soc/intel/alderlake/fsp_params.c
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@ -1068,6 +1068,15 @@ static void fill_fsps_fivr_params(FSP_S_CONFIG *s_cfg,
s_cfg->PchFivrExtVnnRailIccMaximum = s_cfg->PchFivrExtVnnRailIccMaximum =
config->ext_fivr_settings.vnn_icc_max_ma; config->ext_fivr_settings.vnn_icc_max_ma;
#if CONFIG(SOC_INTEL_ALDERLAKE_PCH_N)
/* Enable the FIVR VCCST ICCMax Control for ADL-N.
* TODO:Right now the UPD is update in partial headers for only ADL-N and when its
* updated for ADL-P then we will remove the config since this needs to be enabled for
* all the Alderlake platforms.
*/
s_cfg->PchFivrVccstIccMaxControl = 1;
#endif
} }
static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg, static void fill_fsps_fivr_rfi_params(FSP_S_CONFIG *s_cfg,