Add check_member macro to allow clean and easy struct offset checking

This patch adds a new static assertion macro that can be used to check
the offsets in structures that overlay register sets at compile time. It
uses the _Static_assert() declaration from the new ISO C11 standard,
which is supported (even without -std=c11) by GCC after version 4.6.
(There is supposedly also support in clang, although I haven't tried
it... let's deal with compiler issues when/if they turn up.)

I've added it to all structures for our current ARM SoCs for now, and I
think every new register overlay we add going forward should use them
(at least for the last member, but feel free to add more if you think
it's useful).

Change-Id: If32510e7049739ad05618d363a854dc372d64386
Signed-off-by: Julius Werner <jwerner@chromium.org>
Reviewed-on: https://chromium-review.googlesource.com/179412
Reviewed-by: David Hendricks <dhendrix@chromium.org>
Reviewed-by: Stefan Reinauer <reinauer@chromium.org>
(cherry picked from commit cef5fa13c31375a316ca4556c0039b17c8ea7900)
Signed-off-by: Isaac Christensen <isaac.christensen@se-eng.com>
Reviewed-on: http://review.coreboot.org/6905
Tested-by: build bot (Jenkins)

src/include/stddef.h

@@ -28,6 +28,10 @@ typedef unsigned int wint_t;
 
 #define offsetof(TYPE, MEMBER) ((size_t) &((TYPE *)0)->MEMBER)
 
+#define check_member(structure, member, offset) _Static_assert( \
+	offsetof(struct structure, member) == offset, \
+	"`struct " #structure "` offset for `" #member "` is not " #offset )
+
 #ifdef __PRE_RAM__
 #define ROMSTAGE_CONST const
 #else

src/soc/nvidia/tegra/dc.h

@@ -89,6 +89,7 @@ struct dc_cmd_reg {
 	u32 disp_win_header;		/* _CMD_DISPLAY_WINDOW_HEADER_0 */
 	u32 reg_act_ctrl;		/* _CMD_REG_ACT_CONTROL_0 */
 };
+check_member(dc_cmd_reg, reg_act_ctrl, 0x43 * 4);
 
 enum {
 	PIN_REG_COUNT		= 4,
@@ -137,6 +138,7 @@ struct dc_com_reg {
 	u32 gpio_debounce_cnt;		/* _COM_GPIO_DEBOUNCE_COUNTER_0 */
 	u32 crc_checksum_latched;	/* _COM_CRC_CHECKSUM_LATCHED_0 */
 };
+check_member(dc_com_reg, crc_checksum_latched, (0x329 - 0x300) * 4);
 
 enum dc_disp_h_pulse_pos {
 	H_PULSE0_POSITION_A,
@@ -272,6 +274,7 @@ struct dc_disp_reg {
 	u32 dac_crt_ctrl;		/* _DISP_DAC_CRT_CTRL_0 */
 	u32 disp_misc_ctrl;		/* _DISP_DISP_MISC_CONTROL_0 */
 };
+check_member(dc_disp_reg, disp_misc_ctrl, (0x4c1 - 0x400) * 4);
 
 enum dc_winc_filter_p {
 	WINC_FILTER_COUNT	= 0x10,
@@ -305,6 +308,7 @@ struct dc_winc_reg {
 	/* Address 0x619 ~ 0x628: _WINC_V_FILTER_P00~0F_0 */
 	u32 v_filter_p[WINC_FILTER_COUNT];
 };
+check_member(dc_winc_reg, v_filter_p, (0x619 - 0x500) * 4);
 
 /* WIN A/B/C Register 0x700 ~ 0x714*/
 struct dc_win_reg {
@@ -331,6 +335,7 @@ struct dc_win_reg {
 	u32 blend_3win_xy;		/* _WIN_BLEND_3WIN_XY_0 */
 	u32 hp_fetch_ctrl;		/* _WIN_HP_FETCH_CONTROL_0 */
 };
+check_member(dc_win_reg, hp_fetch_ctrl, (0x714 - 0x700) * 4);
 
 /* WINBUF A/B/C Register 0x800 ~ 0x80a */
 struct dc_winbuf_reg {
@@ -347,6 +352,7 @@ struct dc_winbuf_reg {
 	u32 addr_v_offset_ns;		/* _WINBUF_ADDR_V_OFFSET_NS_0 */
 	u32 uflow_status;		/* _WINBUF_UFLOW_STATUS_0 */
 };
+check_member(dc_winbuf_reg, uflow_status, (0x80a - 0x800) * 4);
 
 /* Display Controller (DC_) regs */
 struct display_controller {
@@ -367,6 +373,7 @@ struct display_controller {
 
 	struct dc_winbuf_reg winbuf;	/* WINBUF A/B/C 0x800 ~ 0x80a */
 };
+check_member(display_controller, winbuf, 0x800 * 4);
 
 #define BIT(pos)	(1U << pos)
 

src/soc/nvidia/tegra/i2c.h

@@ -149,5 +149,6 @@ struct tegra_i2c_regs {
 	uint32_t bus_clear_status;
 	uint32_t spare;
 };
+check_member(tegra_i2c_regs, bus_clear_status, 0x88);
 
 #endif	/* __SOC_NVIDIA_TEGRA_I2C_H__ */

src/soc/nvidia/tegra/usb.h

@@ -44,6 +44,7 @@ struct utmip_ctlr {
 	u32 misc_sts;
 	u32 pmc_wakeup;
 };
+check_member(utmip_ctlr, pmc_wakeup, 0x84c - 0x800);
 
 struct usb_ctlr {
 	u32 id;
@@ -108,6 +109,7 @@ struct usb_ctlr {
 	u32 _rsv14[207];
 	struct utmip_ctlr utmip;	/* 0x800 */
 };
+check_member(usb_ctlr, utmip, 0x800);
 
 enum usb_phy_type {		/* For use in lpm_ctrl[31:29] */
 	USB_PHY_UTMIP = 0,

src/soc/nvidia/tegra124/clk_rst.h

@@ -295,6 +295,7 @@ struct  __attribute__ ((__packed__)) clk_rst_ctlr {
 	u32 clk_src_emc_latency;	/* _CLK_SOURCE_EMC_LATENCY  0x640 */
 	u32 clk_src_soc_therm;		/* _CLK_SOURCE_SOC_THERM    0x644 */
 };
+check_member(clk_rst_ctlr, clk_src_soc_therm, 0x644);
 
 #define TEGRA_DEV_L			0
 #define TEGRA_DEV_H			1

src/soc/nvidia/tegra124/dma.h

@@ -70,6 +70,7 @@ struct apb_dma {
 	u32 chan_wr_reg3;	/* 0x50 */
 	u32 channel_swid1;	/* 0x54 */
 } __attribute__((packed));
+check_member(apb_dma, channel_swid1, 0x54);
 
 /*
  * Naming in the doc included a superfluous _CHANNEL_n_ for
@@ -167,6 +168,7 @@ struct apb_dma_channel_regs {
 	u32 wcount;		/* 0x20 */
 	u32 word_transfer;	/* 0x24 */
 } __attribute__((packed));
+check_member(apb_dma_channel_regs, word_transfer, 0x24);
 
 struct apb_dma_channel {
 	const int num;

src/soc/nvidia/tegra124/flow.h

@@ -36,6 +36,7 @@ struct flow_ctlr {
 	u32 mpid;		/* offset 0x3c */
 	u32 ram_repair;		/* offset 0x40 */
 };
+check_member(flow_ctlr, ram_repair, 0x40);
 
 enum {
 	FLOW_MODE_SHIFT = 29,

src/soc/nvidia/tegra124/pmc.h

@@ -156,6 +156,7 @@ struct tegra_pmc_regs {
 	u32 secure_scratch8[24 - 8];
 	u32 scratch56[120 - 56];
 };
+check_member(tegra_pmc_regs, scratch56, 0x340);
 
 enum {
 	PMC_PWRGATE_TOGGLE_PARTID_MASK = 0x1f,

src/soc/nvidia/tegra124/spi.h

@@ -39,6 +39,7 @@ struct tegra_spi_regs {
 	u32 rx_fifo;		/* 0x188: SPI_FIFO2 */
 	u32 spare_ctl;		/* 0x18c: SPI_SPARE_CTRL */
 } __attribute__((packed));
+check_member(tegra_spi_regs, spare_ctl, 0x18c);
 
 enum spi_xfer_mode {
 	XFER_MODE_NONE = 0,

src/soc/nvidia/tegra124/sysctr.h

@@ -50,5 +50,6 @@ struct sysctr_regs {
 	uint32_t counterid10;
 	uint32_t counterid11;
 };
+check_member(sysctr_regs, counterid11, 0xffc);
 
 #endif	/* __SOC_NVIDIA_TEGRA124_SYSCTR_H__ */

src/soc/samsung/exynos5250/clk.h

@@ -431,7 +431,7 @@ struct exynos5_clock {
 	unsigned int	clkout_cmu_r1x_div_stat;
 	unsigned char	res98[0x3608];
 
-	unsigned int	bpll_lock;		/* base + 0x2000c */
+	unsigned int	bpll_lock;		/* base + 0x20010 */
 	unsigned char	res99[0xfc];
 	unsigned int	bpll_con0;
 	unsigned int	bpll_con1;
@@ -461,6 +461,7 @@ struct exynos5_clock {
 	unsigned int	pll_div2_sel;
 	unsigned char	res109b[0xf5e4];
 };
+check_member(exynos5_clock, pll_div2_sel, 0x20a24);
 
 static struct exynos5_clock * const exynos_clock = (void *)EXYNOS5_CLOCK_BASE;
 
@@ -521,6 +522,7 @@ struct exynos5_mct {
 	uint8_t		reserved14[0x8];
 	uint32_t	l1_wstat;
 };
+check_member(exynos5_mct, l1_wstat, 0x440);
 
 static struct exynos5_mct * const exynos_mct =
 		(void *)EXYNOS5_MULTI_CORE_TIMER_BASE;

src/soc/samsung/exynos5250/dmc.h

@@ -115,6 +115,7 @@ struct exynos5_dmc {
 	unsigned char res34[0xc];
 	unsigned int pmcnt3_ppc_a;
 };
+check_member(exynos5_dmc, pmcnt3_ppc_a, 0xe140);
 
 static struct exynos5_dmc * const exynos_dmc = (void *)EXYNOS5_DMC_CTRL_BASE;
 
@@ -136,7 +137,7 @@ struct exynos5_phy_control {
 	unsigned int phy_con14;
 	unsigned int phy_con15;
 	unsigned int phy_con16;
-	unsigned char res4[4];
+	unsigned char res4[4];	/* NOT a mistake. Yes, it doesn't make sense. */
 	unsigned int phy_con17;
 	unsigned int phy_con18;
 	unsigned int phy_con19;
@@ -164,6 +165,7 @@ struct exynos5_phy_control {
 	unsigned int phy_con41;
 	unsigned int phy_con42;
 };
+check_member(exynos5_phy_control, phy_con42, 0xac);
 
 static struct exynos5_phy_control * const exynos_phy0_control =
 		(void *)EXYNOS5_DMC_PHY0_BASE;

src/soc/samsung/exynos5250/dp.h

@@ -163,6 +163,7 @@ struct exynos5_dp {
 	u8	res21[0x3c];
 	u32	soc_general_ctl;
 };
+check_member(exynos5_dp, soc_general_ctl, 0x800);
 
 static struct exynos5_dp * const exynos_dp0 = (void *)EXYNOS5_DP0_BASE;
 static struct exynos5_dp * const exynos_dp1 = (void *)EXYNOS5_DP1_BASE;

src/soc/samsung/exynos5250/dsim.h

@@ -48,6 +48,7 @@ struct exynos5_dsim {
 	unsigned int phyacchr;
 	unsigned int phyacchr1;
 };
+check_member(exynos5_dsim, phyacchr1, 0x54);
 
 #define ENABLE		1
 #define DISABLE		0

src/soc/samsung/exynos5250/fimd.h

@@ -61,6 +61,7 @@ struct exynos5_fimd {
 	unsigned char res9[0x18];
 	unsigned int dpclkcon;
 };
+check_member(exynos5_fimd, dpclkcon, 0x27c);
 
 static struct exynos5_fimd * const exynos_fimd = (void *)EXYNOS5_FIMD_BASE;
 
@@ -109,6 +110,7 @@ struct exynos5_disp_ctrl {
 	unsigned char res2[0x184];
 	unsigned int trigcon;
 };
+check_member(exynos5_disp_ctrl, trigcon, 0x1a4);
 
 static struct exynos5_disp_ctrl * const exynos_disp_ctrl =
 		(void *)EXYNOS5_DISP1_CTRL_BASE;

src/soc/samsung/exynos5250/power.h

@@ -64,6 +64,7 @@ struct exynos5_power {
         uint8_t         reserved8[0x1e0];
 	uint32_t	ps_hold_ctrl;		/* 0x330c */
 } __attribute__ ((__packed__));
+check_member(exynos5_power, ps_hold_ctrl, 0x330c);
 
 static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;
 

src/soc/samsung/exynos5250/spi.h

@@ -39,6 +39,7 @@ struct exynos_spi {
 	unsigned int		fb_clk;		/* 0x2c */
 	unsigned char		padding[0xffd0];
 };
+check_member(exynos_spi, fb_clk, 0x2c);
 
 #define EXYNOS_SPI_MAX_FREQ	50000000
 

src/soc/samsung/exynos5250/sysreg.h

@@ -32,6 +32,7 @@ struct exynos5_sysreg {
 	unsigned char	res2[0x18];
 	unsigned int	usb20_phy_cfg;
 };
+check_member(exynos5_sysreg, usb20_phy_cfg, 0x230);
 
 static struct exynos5_sysreg * const exynos_sysreg =
 		(void *)EXYNOS5_SYSREG_BASE;

src/soc/samsung/exynos5250/tmu.h

@@ -57,6 +57,7 @@ struct tmu_reg {
 	unsigned rsvd15;
 	unsigned emul_con;
 };
+check_member(tmu_reg, emul_con, 0x80);
 
 enum tmu_status_t {
 	TMU_STATUS_INIT = 0,

src/soc/samsung/exynos5250/trustzone.h

@@ -75,6 +75,7 @@ struct exynos_tzpc {
 	u32 pcellid2;
 	u32 pcellid3;
 };
+check_member(exynos_tzpc, pcellid3, 0xffc);
 
 void trustzone_init(void);
 

src/soc/samsung/exynos5250/uart.h

@@ -21,12 +21,6 @@
 #ifndef CPU_SAMSUNG_EXYNOS5250_UART_H
 #define CPU_SAMSUNG_EXYNOS5250_UART_H
 
-/* baudrate rest value */
-union br_rest {
-	unsigned short	slot;		/* udivslot */
-	unsigned char	value;		/* ufracval */
-};
-
 struct s5p_uart {
 	unsigned int	ulcon;
 	unsigned int	ucon;
@@ -41,8 +35,8 @@ struct s5p_uart {
 	unsigned char	urxh;
 	unsigned char	res2[3];
 	unsigned int	ubrdiv;
-	union br_rest	rest;
 	unsigned char	res3[0xffd0];
 };
+check_member(s5p_uart, ubrdiv, 0x28);
 
 #endif

src/soc/samsung/exynos5250/usb.h

@@ -58,6 +58,7 @@ struct exynos5_usb_host_phy {
         uint8_t reserved4[4];
         uint32_t usbotgtune;
 };
+check_member(exynos5_usb_host_phy, usbotgtune, 0x40);
 
 static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
 		(void *)EXYNOS5_USB_HOST_PHY_BASE;
@@ -81,6 +82,7 @@ struct exynos5_usb_drd_phy {
 	uint32_t linkhcbelt;
 	uint32_t linkport;
 };
+check_member(exynos5_usb_drd_phy, linkport, 0x44);
 
 static struct exynos5_usb_drd_phy * const exynos_usb_drd_phy =
 		(void *)EXYNOS5_USB_DRD_PHY_BASE;
@@ -121,6 +123,7 @@ struct exynos5_usb_drd_dwc3 {
 	uint32_t usb3pipectl;
 	uint8_t reserved6[60];
 };
+check_member(exynos5_usb_drd_dwc3, usb3pipectl, 0x1c0);
 
 static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd_dwc3 =
 		(void *)EXYNOS5_USB_DRD_DWC3_BASE;

src/soc/samsung/exynos5420/clk.h

@@ -596,6 +596,7 @@ struct exynos5420_clock {
 	uint8_t		res148[0x1fdc];
 	uint32_t	cmu_kfc_version;	/* 0x1003bff0 */
 };
+check_member(exynos5420_clock, cmu_kfc_version, 0x2bff0);
 
 static struct exynos5420_clock * const exynos_clock =
 		(void *)EXYNOS5_CLOCK_BASE;
@@ -657,6 +658,7 @@ struct exynos5_mct {
 	uint8_t		reserved14[0x8];
 	uint32_t	l1_wstat;
 };
+check_member(exynos5_mct, l1_wstat, 0x440);
 
 static struct exynos5_mct * const exynos_mct =
 		(void *)EXYNOS5_MULTI_CORE_TIMER_BASE;

src/soc/samsung/exynos5420/dmc.h

@@ -206,6 +206,7 @@ struct exynos5_dmc {
 	uint8_t res41[0xc];
 	uint32_t pmcnt3_ppc;	/* 0xe140 */
 } __attribute__((packed));
+check_member(exynos5_dmc, pmcnt3_ppc, 0xe140);
 
 static struct exynos5_dmc * const exynos_drex0 = (void *)EXYNOS5420_DMC_DREXI_0;
 static struct exynos5_dmc * const exynos_drex1 = (void *)EXYNOS5420_DMC_DREXI_1;
@@ -228,7 +229,7 @@ struct exynos5_phy_control {
 	uint32_t phy_con14;
 	uint32_t phy_con15;
 	uint32_t phy_con16;
-	uint8_t res4[4];
+	uint8_t res4[4];	/* NOT a mistake. Yes, it doesn't make sense. */
 	uint32_t phy_con17;
 	uint32_t phy_con18;
 	uint32_t phy_con19;
@@ -256,6 +257,7 @@ struct exynos5_phy_control {
 	uint32_t phy_con41;
 	uint32_t phy_con42;
 } __attribute__((packed));
+check_member(exynos5_phy_control, phy_con42, 0xac);
 
 static struct exynos5_phy_control * const exynos_phy0_control =
 		(void *)EXYNOS5_DMC_PHY0_BASE;

src/soc/samsung/exynos5420/dp.h

@@ -210,6 +210,7 @@ struct exynos_dp {
 	u32	test_pattern_gen_en;
 	u32	test_pattern_gen_ctrl;
 };
+check_member(exynos_dp, phy_ctrl, 0x924);
 
 static struct exynos_dp * const exynos_dp0 = (void *)EXYNOS5_DP0_BASE;
 static struct exynos_dp * const exynos_dp1 = (void *)EXYNOS5_DP1_BASE;
@@ -882,7 +883,7 @@ struct exynos_fb {
 	u8 res16[16];
 	u32 dp_mie_clkcon;
 };
-
+/* TODO: can't decipher this, someone add a check_member() please */
 
 /* LCD IF register offset */
 #define EXYNOS5_LCD_IF_BASE_OFFSET			0x20000

src/soc/samsung/exynos5420/dsim.h

@@ -48,6 +48,7 @@ struct exynos5_dsim {
 	unsigned int phyacchr;
 	unsigned int phyacchr1;
 };
+check_member(exynos5_dsim, phyacchr1, 0x54);
 
 #define ENABLE		1
 #define DISABLE		0

src/soc/samsung/exynos5420/fimd.h

@@ -61,6 +61,7 @@ struct exynos5_fimd {
 	u8 res9[0x18];
 	u32 dpclkcon;
 };
+check_member(exynos5_fimd, dpclkcon, 0x27c);
 
 #define W0_SHADOW_PROTECT	(0x1 << 10)
 #define COMPKEY_F		0xffffff
@@ -107,6 +108,7 @@ struct exynos5_disp_ctrl {
 	u8 res2[0x184];
 	u32 trigcon;
 };
+check_member(exynos5_disp_ctrl, trigcon, 0x1a4);
 
 #define VCLK_RISING_EDGE		(1 << 7)
 #define VCLK_RUNNING			(1 << 9)

src/soc/samsung/exynos5420/i2c.h

@@ -61,6 +61,7 @@ struct exynos5_hsi2c {
 	u32	usi_timing_sla;
 	u32	i2c_addr;
 } __attribute__ ((packed));
+check_member(exynos5_hsi2c, i2c_addr, 0x70);
 
 struct s3c24x0_i2c_bus {
 	int bus_num;

src/soc/samsung/exynos5420/power.h

@@ -77,6 +77,7 @@ struct exynos5_power {
 	uint8_t         reservedC[0x120];
 	uint32_t	ps_hold_ctrl;		/* 0x330c */
 } __attribute__ ((__packed__));
+check_member(exynos5_power, ps_hold_ctrl, 0x330c);
 
 static struct exynos5_power * const exynos_power = (void*)EXYNOS5_POWER_BASE;
 

src/soc/samsung/exynos5420/spi.h

@@ -39,6 +39,7 @@ struct exynos_spi {
 	unsigned int		fb_clk;		/* 0x2c */
 	unsigned char		padding[0xffd0];
 };
+check_member(exynos_spi, fb_clk, 0x2c);
 
 #define EXYNOS_SPI_MAX_FREQ	50000000
 

src/soc/samsung/exynos5420/sysreg.h

@@ -32,6 +32,7 @@ struct exynos5_sysreg {
 	unsigned char	res2[0x18];
 	unsigned int	usb20_phy_cfg;
 };
+check_member(exynos5_sysreg, usb20_phy_cfg, 0x230);
 
 static struct exynos5_sysreg * const exynos_sysreg =
 		(void *)EXYNOS5_SYSREG_BASE;

src/soc/samsung/exynos5420/tmu.h

@@ -57,6 +57,7 @@ struct tmu_reg {
 	unsigned rsvd15;
 	unsigned emul_con;
 };
+check_member(tmu_reg, emul_con, 0x80);
 
 enum tmu_status_t {
 	TMU_STATUS_INIT = 0,

src/soc/samsung/exynos5420/trustzone.h

@@ -75,6 +75,7 @@ struct exynos_tzpc {
 	u32 pcellid2;
 	u32 pcellid3;
 };
+check_member(exynos_tzpc, pcellid3, 0xffc);
 
 void trustzone_init(void);
 

src/soc/samsung/exynos5420/uart.h

@@ -21,12 +21,6 @@
 #ifndef CPU_SAMSUNG_EXYNOS5420_UART_H
 #define CPU_SAMSUNG_EXYNOS5420_UART_H
 
-/* baudrate rest value */
-union br_rest {
-	unsigned short	slot;		/* udivslot */
-	unsigned char	value;		/* ufracval */
-};
-
 struct s5p_uart {
 	unsigned int	ulcon;
 	unsigned int	ucon;
@@ -41,8 +35,8 @@ struct s5p_uart {
 	unsigned char	urxh;
 	unsigned char	res2[3];
 	unsigned int	ubrdiv;
-	union br_rest	rest;
 	unsigned char	res3[0xffd0];
 };
+check_member(s5p_uart, ubrdiv, 0x28);
 
 #endif

src/soc/samsung/exynos5420/usb.h

@@ -58,6 +58,7 @@ struct exynos5_usb_host_phy {
         uint8_t reserved4[4];
         uint32_t usbotgtune;
 };
+check_member(exynos5_usb_host_phy, usbotgtune, 0x40);
 
 static struct exynos5_usb_host_phy * const exynos_usb_host_phy =
 		(void *)EXYNOS5_USB_HOST_PHY_BASE;
@@ -81,6 +82,7 @@ struct exynos5_usb_drd_phy {
 	uint32_t linkhcbelt;
 	uint32_t linkport;
 };
+check_member(exynos5_usb_drd_phy, linkport, 0x44);
 
 static struct exynos5_usb_drd_phy * const exynos_usb_drd0_phy =
 		(void *)EXYNOS5420_USB_DRD0_PHY_BASE;
@@ -123,6 +125,7 @@ struct exynos5_usb_drd_dwc3 {
 	uint32_t usb3pipectl;
 	uint8_t reserved6[60];
 };
+check_member(exynos5_usb_drd_dwc3, usb3pipectl, 0x1c0);
 
 static struct exynos5_usb_drd_dwc3 * const exynos_usb_drd0_dwc3 =
 		(void *)EXYNOS5420_USB_DRD0_DWC3_BASE;