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broadwell: Fix incorrect SATA port map mask 

WPT-LP has 4 SATA ports. Current code assumes 6 SATA ports and as a result,
some reserved bits are written with 1. No specific issue has been observed
so far.

BUG=None
BRANCH=None
TEST=Verify SATA PCI configure space dump on Auron

Change-Id: I737719b3d5cd788158cd5b6991405ba098be4078
Signed-off-by: Stefan Reinauer <reinauer@chromium.org>
Original-Commit-Id: 2b55587a74ac5d45354dc123937b562290468855
Original-Change-Id: I9c53ac86e2bf72901647bd2cfa48ac0ce31abea0
Original-Signed-off-by: Wenkai Du <wenkai.du@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/233661
Original-Reviewed-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/9479
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
This commit is contained in:
Wenkai Du 2014-12-05 14:04:10 -08:00 committed by Patrick Georgi
parent 8c916ec834
commit 038cce2c2e
1 changed files with 3 additions and 3 deletions
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6
src/soc/intel/broadwell/sata.c
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@ -65,7 +65,7 @@ static void sata_init(struct device *dev)
/* for AHCI, Port Enable is managed in memory mapped space */
reg16 = pci_read_config16(dev, 0x92);
reg16 &= ~0x3f;
reg16 &= ~0xf;
reg16 |= 0x8000 | config->sata_port_map;
pci_write_config16(dev, 0x92, reg16);
udelay(2);
@ -84,7 +84,7 @@ static void sata_init(struct device *dev)
/* SATA Initialization register */
reg32 = 0x183;
reg32 |= (config->sata_port_map ^ 0x3f) << 24;
reg32 |= (config->sata_port_map ^ 0xf) << 24;
reg32 |= (config->sata_devslp_mux & 1) << 15;
pci_write_config32(dev, 0x94, reg32);
@ -237,7 +237,7 @@ static void sata_enable(device_t dev)
config_t *config = dev->chip_info;
u16 map = 0x0060;
map |= (config->sata_port_map ^ 0x3f) << 8;
map |= (config->sata_port_map ^ 0xf) << 8;
pci_write_config16(dev, 0x90, map);
}