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I/O ports are 16bit, so change 'unsigned long port_base' to 'u16 port_base'. 

Also, use more readable #defines instead of hardcoded config ports for
PM/PM2 related functions, and simplify them a bit.

Build-tested with the AMD dbm690t target.

Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de>
Acked-by: Marc Jones <marc.jones@amd.com>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3680 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Uwe Hermann 2008-10-21 16:27:38 +00:00
parent 657a6dc390
commit 039255c59c
3 changed files with 17 additions and 17 deletions
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16
src/southbridge/amd/sb600/sb600.c
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@ -60,13 +60,13 @@ void set_sm_enable_bits(device_t sm_dev, u32 reg_pos, u32 mask, u32 val)
} }
} }
static void pmio_write_index(unsigned long port_base, u8 reg, u8 value) static void pmio_write_index(u16 port_base, u8 reg, u8 value)
{ {
outb(reg, port_base); outb(reg, port_base);
outb(value, port_base + 1); outb(value, port_base + 1);
} }
static u8 pmio_read_index(unsigned long port_base, u8 reg) static u8 pmio_read_index(u16 port_base, u8 reg)
{ {
outb(reg, port_base); outb(reg, port_base);
return inb(port_base + 1); return inb(port_base + 1);
@ -74,26 +74,22 @@ static u8 pmio_read_index(unsigned long port_base, u8 reg)
void pm_iowrite(u8 reg, u8 value) void pm_iowrite(u8 reg, u8 value)
{ {
unsigned long port_base = 0xcd6; pmio_write_index(PM_INDEX, reg, value);
pmio_write_index(port_base, reg, value);
} }
u8 pm_ioread(u8 reg) u8 pm_ioread(u8 reg)
{ {
unsigned long port_base = 0xcd6; return pmio_read_index(PM_INDEX, reg);
return pmio_read_index(port_base, reg);
} }
void pm2_iowrite(u8 reg, u8 value) void pm2_iowrite(u8 reg, u8 value)
{ {
unsigned long port_base = 0xcd0; pmio_write_index(PM2_INDEX, reg, value);
pmio_write_index(port_base, reg, value);
} }
u8 pm2_ioread(u8 reg) u8 pm2_ioread(u8 reg)
{ {
unsigned long port_base = 0xcd0; return pmio_read_index(PM2_INDEX, reg);
return pmio_read_index(port_base, reg);
} }
static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos, static void set_pmio_enable_bits(device_t sm_dev, u32 reg_pos,

6
src/southbridge/amd/sb600/sb600.h
View File

@ -23,6 +23,12 @@
#include <device/pci_ids.h> #include <device/pci_ids.h>
#include "chip.h" #include "chip.h"
/* Power management index/data registers */
#define PM_INDEX 0xcd6
#define PM_DATA 0xcd7
#define PM2_INDEX 0xcd0
#define PM2_DATA 0xcd1
extern void pm_iowrite(u8 reg, u8 value); extern void pm_iowrite(u8 reg, u8 value);
extern u8 pm_ioread(u8 reg); extern u8 pm_ioread(u8 reg);
extern void pm2_iowrite(u8 reg, u8 value); extern void pm2_iowrite(u8 reg, u8 value);

12
src/southbridge/amd/sb600/sb600_early_setup.c
View File

@ -18,24 +18,22 @@
*/ */
#include <arch/cpu.h> #include <arch/cpu.h>
#include "sb600.h"
#include "sb600_smbus.c" #include "sb600_smbus.c"
#define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */ #define SMBUS_IO_BASE 0x1000 /* Is it a temporary SMBus I/O base address? */
/*SIZE 0x40 */ /*SIZE 0x40 */
/* Copied from sb600.c
* 0xCD6-0xCD7 is power management I/O register.*/
static void pmio_write(u8 reg, u8 value) static void pmio_write(u8 reg, u8 value)
{ {
outb(reg, 0xCD6); outb(reg, PM_INDEX);
outb(value, 0xCD6 + 1); outb(value, PM_INDEX + 1);
} }
static u8 pmio_read(u8 reg) static u8 pmio_read(u8 reg)
{ {
outb(reg, 0xCD6); outb(reg, PM_INDEX);
return inb(0xCD6 + 1); return inb(PM_INDEX + 1);
} }
/* Get SB ASIC Revision.*/ /* Get SB ASIC Revision.*/