adding 855pm
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@1629 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Ronald G. Minnich
parent
198409afe0
commit
03935036ab
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@ -0,0 +1,4 @@
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config chip.h
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object northbridge.o
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#driver misc_control.o
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@ -0,0 +1,5 @@
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struct northbridge_intel_855pm_config
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{
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};
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extern struct chip_control northbridge_intel_855pm_control;
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@ -0,0 +1,164 @@
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/*
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* generic K8 debug code, used by mainboard specific auto.c
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*
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*/
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#if 1
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static void print_debug_pci_dev(unsigned dev)
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{
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print_debug("PCI: ");
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print_debug_hex8((dev >> 16) & 0xff);
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print_debug_char(':');
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print_debug_hex8((dev >> 11) & 0x1f);
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print_debug_char('.');
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print_debug_hex8((dev >> 8) & 7);
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}
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static void print_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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}
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}
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static void dump_pci_device(unsigned dev)
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{
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int i;
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print_debug_pci_dev(dev);
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print_debug("\r\n");
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for(i = 0; i <= 255; i++) {
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unsigned char val;
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if ((i & 0x0f) == 0) {
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print_debug_hex8(i);
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print_debug_char(':');
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}
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val = pci_read_config8(dev, i);
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print_debug_char(' ');
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print_debug_hex8(val);
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if ((i & 0x0f) == 0x0f) {
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print_debug("\r\n");
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}
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}
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}
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static void dump_pci_devices(void)
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{
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device_t dev;
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for(dev = PCI_DEV(0, 0, 0);
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dev <= PCI_DEV(0, 0x1f, 0x7);
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dev += PCI_DEV(0,0,1)) {
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uint32_t id;
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id = pci_read_config32(dev, PCI_VENDOR_ID);
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if (((id & 0xffff) == 0x0000) || ((id & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0xffff) ||
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(((id >> 16) & 0xffff) == 0x0000)) {
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continue;
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}
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dump_pci_device(dev);
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}
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}
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static void dump_spd_registers(const struct mem_controller *ctrl)
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{
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int i;
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print_debug("\r\n");
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for(i = 0; i < 4; i++) {
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unsigned device;
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device = ctrl->channel0[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".0: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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#if 0
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device = ctrl->channel1[i];
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if (device) {
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int j;
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print_debug("dimm: ");
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print_debug_hex8(i);
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print_debug(".1: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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#endif
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}
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}
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static void dump_smbus_registers(void)
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{
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int i;
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print_debug("\r\n");
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for(i = 1; i < 0x80; i++) {
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unsigned device;
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device = i;
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int j;
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print_debug("smbus: ");
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print_debug_hex8(device);
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for(j = 0; j < 256; j++) {
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int status;
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unsigned char byte;
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if ((j & 0xf) == 0) {
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print_debug("\r\n");
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print_debug_hex8(j);
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print_debug(": ");
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}
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status = smbus_read_byte(device, j);
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if (status < 0) {
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print_debug("bad device\r\n");
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break;
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}
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byte = status & 0xff;
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print_debug_hex8(byte);
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print_debug_char(' ');
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}
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print_debug("\r\n");
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}
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}
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#endif
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@ -0,0 +1,151 @@
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#include <console/console.h>
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#include <arch/io.h>
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#include <stdint.h>
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#include <mem.h>
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#include <part/sizeram.h>
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#include <device/device.h>
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#include <device/pci.h>
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#include <device/chip.h>
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#include <stdlib.h>
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#include <string.h>
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#include <bitops.h>
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#include "chip.h"
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struct mem_range *sizeram(void)
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{
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static struct mem_range mem[4];
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/* the units of tolm are 64 KB */
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/* the units of drb16 are 64 MB */
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uint16_t tolm, remapbase, remaplimit, drb16;
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uint16_t tolm_r, remapbase_r, remaplimit_r;
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uint8_t drb;
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int remap_high;
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device_t dev;
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dev = dev_find_slot(0, 0); // d0f0
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if (!dev) {
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printk_err("Cannot find PCI: 0:0\n");
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return 0;
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}
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/* Calculate and report the top of low memory and
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* any remapping.
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*/
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/* Test if the remap memory high option is set */
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remap_high = 0;
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// if(get_option(&remap_high, "remap_memory_high")){
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// remap_high = 0;
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// }
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printk_debug("remap_high is %d\n", remap_high);
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/* get out the value of the highest DRB. This tells the end of
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* physical memory. The units are ticks of 64 MB i.e. 1 means
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* 64 MB.
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*/
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drb = pci_read_config8(dev, 0x67);
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drb16 = (uint16_t)drb;
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if(remap_high && (drb16 > 0x08)) {
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/* We only come here if we have at least 512MB of memory,
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* so it is safe to hard code tolm.
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* 0x2000 means 512MB
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*/
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tolm = 0x2000;
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/* i.e 0x40 * 0x40 is 0x1000 which is 4 GB */
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if(drb16 > 0x0040) {
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/* There is more than 4GB of memory put
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* the remap window at the end of ram.
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*/
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remapbase = drb16;
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remaplimit = remapbase + 0x38;
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}
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else {
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remapbase = 0x0040;
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remaplimit = remapbase + (drb16-8);
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}
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}
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else {
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tolm = (uint16_t)((dev_root.resource[1].base >> 16)&0x0f800);
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if((tolm>>8) >= (drb16<<2)) {
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tolm = (drb16<<10);
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remapbase = 0x3ff;
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remaplimit = 0;
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}
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else {
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remapbase = drb16;
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remaplimit = remapbase + ((0x0040-(tolm>>10))-1);
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}
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}
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/* Write the ram configruation registers,
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* preserving the reserved bits.
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*/
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tolm_r = pci_read_config16(dev, 0xc4);
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tolm |= (tolm_r & 0x7ff);
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pci_write_config16(dev, 0xc4, tolm);
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remapbase_r = pci_read_config16(dev, 0xc6);
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remapbase |= (remapbase_r & 0xfc00);
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pci_write_config16(dev, 0xc6, remapbase);
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remaplimit_r = pci_read_config16(dev, 0xc8);
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remaplimit |= (remaplimit_r & 0xfc00);
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pci_write_config16(dev, 0xc8, remaplimit);
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#if 0
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printk_debug("mem info tolm = %x, drb = %x, pci_memory_base = %x, remap = %x-%x\n",tolm,drb,pci_memory_base,remapbase,remaplimit);
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#endif
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mem[0].basek = 0;
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mem[0].sizek = 640;
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mem[1].basek = 768;
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/* Convert size in 64K bytes to size in K bytes */
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mem[1].sizek = (tolm << 6) - mem[1].basek;
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mem[2].basek = 0;
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mem[2].sizek = 0;
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if ((drb << 16) > (tolm << 6)) {
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/* We don't need to consider the remap window
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* here because we put it immediately after the
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* rest of ram.
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* All we must do is calculate the amount
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* of unused memory and report it at 4GB.
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*/
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mem[2].basek = 4096*1024;
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mem[2].sizek = (drb << 16) - (tolm << 6);
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}
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mem[3].basek = 0;
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mem[3].sizek = 0;
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return mem;
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}
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static void enumerate(struct chip *chip)
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{
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extern struct device_operations default_pci_ops_bus;
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chip_enumerate(chip);
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chip->dev->ops = &default_pci_ops_bus;
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}
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#if 0
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static void northbridge_init(struct chip *chip, enum chip_pass pass)
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{
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struct northbridge_intel_855pm_config *conf =
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(struct northbridge_intel_855pm_config *)chip->chip_info;
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switch (pass) {
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case CONF_PASS_PRE_PCI:
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break;
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case CONF_PASS_POST_PCI:
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break;
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case CONF_PASS_PRE_BOOT:
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break;
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default:
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/* nothing yet */
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break;
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}
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}
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#endif
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struct chip_control northbridge_intel_855pm_control = {
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.enumerate = enumerate,
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// .enable = northbridge_init,
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.name = "intel E7501 Northbridge",
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};
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File diff suppressed because it is too large
Load Diff
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@ -0,0 +1,12 @@
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#ifndef RAMINIT_H
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#define RAMINIT_H
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#define DIMM_SOCKETS 4
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struct mem_controller {
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device_t d0, d0f1;
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uint16_t channel0[DIMM_SOCKETS];
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uint16_t channel1[DIMM_SOCKETS];
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};
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#endif /* RAMINIT_H */
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@ -0,0 +1,18 @@
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/* Convert to C by yhlu */
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#define MCH_DRC 0x7c
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#define DRC_DONE (1 << 29)
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/* If I have already booted once skip a bunch of initialization */
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/* To see if I have already booted I check to see if memory
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* has been enabled.
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*/
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static int bios_reset_detected(void) {
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uint32_t dword;
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dword = pci_read_config32(PCI_DEV(0, 0, 0), MCH_DRC);
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if( (dword & DRC_DONE) != 0 ) {
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return 1;
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}
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return 0;
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}
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