soc/intel/apollolake: Add GNVS variables and include SGX ASL

- Add GNVS variables for SGX
- include SGX ASL if CONFIG_SOC_INTEL_COMMON_BLOCK_SGX is set
- With this patch SGX ACPI device would get created and kernel SGX
  driver would let loaded

Change-Id: I112cad3cd871082b1884787084c4cc0ebdc7d08f
Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/21965
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>

src/soc/intel/apollolake/acpi/globalnvs.asl

@@ -42,6 +42,9 @@ Field (GNVS, ByteAcc, NoLock, Preserve)
 	SCDP,	8,      // 0x29 - SD_CD GPIO portid
 	SCDO,	8,      // 0x2A - GPIO pad offset relative to the community
 	UIOR,	8,      // 0x2B - UART debug controller init on S3 resume
+	EPCS,   8,      // 0x2C - SGX Enabled status
+	EMNA,   64,     // 0x2D - 0x34 EPC base address
+	ELNG,   64,     // 0x35 - 0x3C EPC Length
 
 	/* ChromeOS stuff (0x100 -> 0xfff, size 0xeff) */
 	Offset (0x100),

src/soc/intel/apollolake/acpi/southbridge.asl

@@ -52,3 +52,8 @@ Scope (\_SB)
 
 /* PCI _OSC */
 #include <soc/intel/common/acpi/pci_osc.asl>
+
+/* SGX */
+#if IS_ENABLED(CONFIG_SOC_INTEL_COMMON_BLOCK_SGX)
+#include <soc/intel/common/acpi/sgx.asl>
+#endif

src/soc/intel/apollolake/include/soc/nvs.h

@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2015 Intel Corp.
+ * Copyright (C) 2015-2017 Intel Corp.
  * (Written by Lance Zhao <lijian.zhao@intel.com> for Intel Corp.)
  *
  * This program is free software; you can redistribute it and/or modify
@@ -44,6 +44,9 @@ typedef struct global_nvs_t {
 	uint8_t		scdo; /* 0x2A - GPIO pad offset relative to the community */
 	uint8_t		uior; /* 0x2B - UART debug controller init on S3
 					 resume */
+	uint8_t		ecps; /* 0x2C - SGX Enabled status */
+	uint64_t	emna; /* 0x2D - 0x34 EPC base address */
+	uint64_t	elng; /* 0x35 - 0x3C EPC Length */
 	uint8_t		unused[212];
 
 	/* ChromeOS specific (0x100 - 0xfff) */