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mb/pcengines/apu2: do not pass enabled PCIe ClockPM to AGESA

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Certain PCIe endpoints cause an exception inside AmdInitMid when PCIe
ClockPM is enabled in AGESA PCIe initialization structures. Disable it
to allow platform to boot with such devices. coreboot driver enables
the ClockPM correctly on such devices anyway.

Signed-off-by: Michał Żygowski <michal.zygowski@3mdeb.com>
Change-Id: I7fb13f915861c26cf773960abb12a3a1c0211cdc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39970
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Michał Żygowski 2020-03-31 13:36:23 +02:00
parent b8b8ec8323
commit 03a3404d5b
1 changed files with 5 additions and 5 deletions
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10
src/mainboard/pcengines/apu2/OemCustomize.c
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@ -35,7 +35,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmL0sL1, AspmL0sL1,
PCIE_PORT3_RESET_ID, PCIE_PORT3_RESET_ID,
ClkPmSupportEnabled) 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 1, PCI Device Number 2, ...) */
{ {
@ -47,7 +47,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmL0sL1, AspmL0sL1,
PCIE_NIC_RESET_ID, PCIE_NIC_RESET_ID,
ClkPmSupportEnabled) 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 2, PCI Device Number 2, ...) */
{ {
@ -59,7 +59,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmL0sL1, AspmL0sL1,
PCIE_NIC_RESET_ID, PCIE_NIC_RESET_ID,
ClkPmSupportEnabled) 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 3, PCI Device Number 2, ...) */
{ {
@ -71,7 +71,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmL0sL1, AspmL0sL1,
PCIE_NIC_RESET_ID, PCIE_NIC_RESET_ID,
ClkPmSupportEnabled) 0)
}, },
/* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */ /* Initialize Port descriptor (PCIe port, Lanes 4-7, PCI Device Number 4, ...) */
{ {
@ -83,7 +83,7 @@ static const PCIe_PORT_DESCRIPTOR PortList[] = {
PcieGenMaxSupported, PcieGenMaxSupported,
AspmL0sL1, AspmL0sL1,
PCIE_GFX_RESET_ID, PCIE_GFX_RESET_ID,
ClkPmSupportEnabled) 0)
} }
}; };