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soc/amd/common/block/smu: rename mailbox register defines

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Since we have the SMN access block now, rename the SMU mailbox interface
registers to clarify that those are in the SMN register space.

Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: Ic5b7093f99eabd3c29610072b186ed156f335bd8
Reviewed-on: https://review.coreboot.org/c/coreboot/+/51400
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Marshall Dawson <marshalldawson3rd@gmail.com>
This commit is contained in:
Felix Held 2021-03-10 23:29:11 +01:00
parent e995684fa1
commit 03a4bfc54d
4 changed files with 14 additions and 20 deletions
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11
src/soc/amd/cezanne/include/soc/smu.h
View file

@ -3,13 +3,10 @@
#ifndef AMD_CEZANNE_SMU_H
#define AMD_CEZANNE_SMU_H
/*
* SMU mailbox register offsets in indirect address space accessed by an index/data pair in
* D0F00 config space.
*/
#define REG_ADDR_MESG_ID 0x3b10528
#define REG_ADDR_MESG_RESP 0x3b10564
#define REG_ADDR_MESG_ARGS_BASE 0x3b10998
/* SMU mailbox register offsets in SMN */
#define SMN_SMU_MESG_ID 0x3b10528
#define SMN_SMU_MESG_RESP 0x3b10564
#define SMN_SMU_MESG_ARGS_BASE 0x3b10998
#define SMU_NUM_ARGS 6

2
src/soc/amd/common/block/include/amdblocks/smu.h
View file

@ -7,7 +7,7 @@
#include <soc/smu.h> /* SoC-dependent definitions for SMU access */
/* Arguments indexed locations are contiguous; the number is SoC-dependent */
#define REG_ADDR_MESG_ARG(x) (REG_ADDR_MESG_ARGS_BASE + ((x) * sizeof(uint32_t)))
#define SMN_SMU_MESG_ARG(x) (SMN_SMU_MESG_ARGS_BASE + ((x) * sizeof(uint32_t)))
struct smu_payload {
uint32_t msg[SMU_NUM_ARGS];

10
src/soc/amd/common/block/smu/smu.c
View file

@ -20,7 +20,7 @@ static int32_t smu_poll_response(bool print_command_duration)
stopwatch_init_msecs_expire(&sw, timeout_ms);
do {
result = smn_read32(REG_ADDR_MESG_RESP);
result = smn_read32(SMN_SMU_MESG_RESP);
if (result) {
if (print_command_duration)
printk(BIOS_SPEW, "SMU command consumed %ld usecs\n",
@ -46,14 +46,14 @@ enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload
return CB_ERR;
/* clear response register */
smn_write32(REG_ADDR_MESG_RESP, 0);
smn_write32(SMN_SMU_MESG_RESP, 0);
/* populate arguments */
for (i = 0 ; i < SMU_NUM_ARGS ; i++)
smn_write32(REG_ADDR_MESG_ARG(i), arg->msg[i]);
smn_write32(SMN_SMU_MESG_ARG(i), arg->msg[i]);
/* send message to SMU */
smn_write32(REG_ADDR_MESG_ID, message_id);
smn_write32(SMN_SMU_MESG_ID, message_id);
/* wait until SMU has processed the message and check if it was successful */
if (smu_poll_response(true) != SMU_MESG_RESP_OK)
@ -61,7 +61,7 @@ enum cb_err send_smu_message(enum smu_message_id message_id, struct smu_payload
/* copy returned values */
for (i = 0 ; i < SMU_NUM_ARGS ; i++)
arg->msg[i] = smn_read32(REG_ADDR_MESG_ARG(i));
arg->msg[i] = smn_read32(SMN_SMU_MESG_ARG(i));
return CB_SUCCESS;
}

11
src/soc/amd/picasso/include/soc/smu.h
View file

@ -3,13 +3,10 @@
#ifndef AMD_PICASSO_SMU_H
#define AMD_PICASSO_SMU_H
/*
* SMU mailbox register offsets in indirect address space accessed by an index/data pair in
* D0F00 config space.
*/
#define REG_ADDR_MESG_ID 0x3b10528
#define REG_ADDR_MESG_RESP 0x3b10564
#define REG_ADDR_MESG_ARGS_BASE 0x3b10998
/* SMU mailbox register offsets in SMN */
#define SMN_SMU_MESG_ID 0x3b10528
#define SMN_SMU_MESG_RESP 0x3b10564
#define SMN_SMU_MESG_ARGS_BASE 0x3b10998
#define SMU_NUM_ARGS 6