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intel/kunimitsu: Clean up GPIOs. 

Some of the pins are not connected/used on kunimitsu board,
this patch will make them "Not connected".

Un-used PINS will controlled by GPIO controller (PMODE = GPIO) and
GPIO TX/RX will be disabled.

BRANCH=none
BUG=none
TEST=Build and booted in kunimitsu.

Change-Id: Iaf0d4806836648808fb91cfc7807c4c1595a5167
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Original-Commit-Id: a7c25ad8ee0d189178124cff20569152b1053488
Original-Change-Id: I3add625b2bf01223cd389c6a5585827ac62dd0c0
Original-Signed-off-by: Pratik Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-on: https://chromium-review.googlesource.com/316700
Original-Commit-Ready: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Tested-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Reviewed-by: Pratikkumar V Prajapati <pratikkumar.v.prajapati@intel.com>
Reviewed-on: https://review.coreboot.org/13629
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Pratik Prajapati 2015-12-07 17:08:07 -08:00 committed by Martin Roth
parent 4852dec1ab
commit 03be2383e7
1 changed files with 79 additions and 79 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

158
src/mainboard/intel/kunimitsu/gpio.h
View File

@ -71,55 +71,55 @@ static const struct pad_config gpio_table[] = {
/* SD_CD_WAKE */ PAD_CFG_GPI(GPP_A7, 20K_PU, DEEP),
/* LPC_CLKRUN */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
/* EC_LPC_CLK */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
/* PCH_LPC_CLK */ /* GPP_A10 */
/* EC_HID_INT */ /* GPP_A11 */
/* ISH_KB_PROX_INT */ PAD_CFG_GPO(GPP_A12, 0, DEEP),
/* PCH_LPC_CLK */ PAD_CFG_NC(GPP_A10),
/* EC_HID_INT */ PAD_CFG_NC(GPP_A11),
/* ISH_KB_PROX_INT */ PAD_CFG_NC(GPP_A12),
/* PCH_SUSPWRACB */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
/* PM_SUS_STAT */ PAD_CFG_NF(GPP_A14, NONE, DEEP, NF1),
/* PM_SUS_STAT */ PAD_CFG_NC(GPP_A14),
/* PCH_SUSACK */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
/* SD_1P8_SEL */ PAD_CFG_NF(GPP_A16, NONE, DEEP, NF1),
/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* ACCEL INTERRUPT */ PAD_CFG_NF(GPP_A18, NONE, DEEP, NF1),
/* ISH_GP1 */ /* GPP_A19 */
/* GYRO_DRDY */ PAD_CFG_NF(GPP_A20, NONE, DEEP, NF1),
/* FLIP_ACCEL_INT */ PAD_CFG_NF(GPP_A21, NONE, DEEP, NF1),
/* GYRO_INT */ PAD_CFG_NF(GPP_A22, NONE, DEEP, NF1),
/* ISH_GP5 */ /* GPP_A23 */
/* CORE_VID0 */ /* GPP_B0 */
/* CORE_VID1 */ /* GPP_B1 */
/* SD_PWR_EN */ PAD_CFG_NF(GPP_A17, NONE, DEEP, NF1),
/* ACCEL INTERRUPT */ PAD_CFG_NC(GPP_A18),
/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
/* GYRO_DRDY */ PAD_CFG_NC(GPP_A20),
/* FLIP_ACCEL_INT */ PAD_CFG_NC(GPP_A21),
/* GYRO_INT */ PAD_CFG_NC(GPP_A22),
/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
/* CORE_VID0 */ PAD_CFG_NC(GPP_B0),
/* CORE_VID1 */ PAD_CFG_NC(GPP_B1),
/* HSJ_MIC_DET */ PAD_CFG_GPI(GPP_B2, NONE, DEEP),
/* TRACKPAD_INT */ PAD_CFG_GPI_APIC(GPP_B3, NONE, DEEP),
/* BT_RF_KILL */ PAD_CFG_GPO(GPP_B4, 0, DEEP),
/* BT_RF_KILL */ PAD_CFG_NC(GPP_B4),
/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES), /* TOUCHPAD WAKE */
/* WIFI_CLK_REQ */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1),
/* KEPLR_CLK_REQ */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1),
/* SRCCLKREQ3# */ /* GPP_B8 */
/* AUDIO_INT_WAK */ PAD_CFG_GPI_ACPI_SCI(GPP_B8, NONE, DEEP, YES),
/* SSD_CLK_REQ */ PAD_CFG_NF(GPP_B9, NONE, DEEP, NF1),
/* SRCCLKREQ5# */ /* GPP_B10 */
/* MPHY_EXT_PWR_GATE */ PAD_CFG_NF(GPP_B11, NONE, DEEP, NF1),
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
/* MPHY_EXT_PWR_GATE */ PAD_CFG_NC(GPP_B11),
/* PM_SLP_S0 */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
/* PCH_PLT_RST */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
/* PCH_BUZZER */ PAD_CFG_GPI(GPP_B14, NONE, DEEP),
/* GSPI0_CS# */ /* GPP_B15 */
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
/* WLAN_PCIE_WAKE */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
/* SSD_PCIE_WAKE */ PAD_CFG_GPI(GPP_B17, NONE, DEEP),
/* GSPI0_MOSI */ /* GPP_B18 */
/* CCODEC_SPI_CS */ PAD_CFG_NF(GPP_B19, NONE, DEEP, NF1),
/* CODEC_SPI_CLK */ PAD_CFG_NF(GPP_B20, NONE, DEEP, NF1),
/* CODEC_SPI_MISO */ PAD_CFG_NF(GPP_B21, NONE, DEEP, NF1),
/* CODEC_SPI_MOSI */ PAD_CFG_NF(GPP_B22, NONE, DEEP, NF1),
/* SM1ALERT# */ PAD_CFG_GPO(GPP_B23, 0, DEEP),
/* SSD_PCIE_WAKE */ PAD_CFG_NC(GPP_B17),
/* GSPI0_MOSI */ PAD_CFG_NC(GPP_B18),
/* CCODEC_SPI_CS */ PAD_CFG_NC(GPP_B19),
/* CODEC_SPI_CLK */ PAD_CFG_NC(GPP_B20),
/* CODEC_SPI_MISO */ PAD_CFG_NC(GPP_B21),
/* CODEC_SPI_MOSI */ PAD_CFG_NC(GPP_B22),
/* SM1ALERT# */ PAD_CFG_NC(GPP_B23),
/* SMB_CLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1),
/* SMB_DATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1),
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
/* M2_WWAN_PWREN */ PAD_CFG_GPO(GPP_C3, 0, DEEP),
/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP),
/* SML0ALERT# */ PAD_CFG_GPO(GPP_C5, 0, DEEP),
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
/* M2_WWAN_PWREN */ PAD_CFG_NC(GPP_C3),
/* SML0DATA */ PAD_CFG_NC(GPP_C4),
/* SML0ALERT# */ PAD_CFG_NC(GPP_C5),
/* EC_IN_RW */ PAD_CFG_GPI(GPP_C6, NONE, DEEP),
/* USB_CTL */ PAD_CFG_GPO(GPP_C7, 1, DEEP),
/* UART0_RXD */ /* GPP_C8 */
/* UART0_TXD */ /* GPP_C9 */
/* NFC_RST* */ PAD_CFG_GPO(GPP_C10, 0, DEEP),
/* USB_CTL */ PAD_CFG_NC(GPP_C7),
/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
/* NFC_RST* */ PAD_CFG_NC(GPP_C10),
/* EN_PP3300_KEPLER */ PAD_CFG_TERM_GPO(GPP_C11, 0, 20K_PD, DEEP),
/* PCH_MEM_CFG0 */ PAD_CFG_GPI(GPP_C12, NONE, DEEP),
/* PCH_MEM_CFG1 */ PAD_CFG_GPI(GPP_C13, NONE, DEEP),
@ -133,66 +133,66 @@ static const struct pad_config gpio_table[] = {
/* GD_UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1),
/* TCH_PNL_PWREN */ PAD_CFG_GPO(GPP_C22, 1, DEEP),
/* SPI_WP_STATUS */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP),
/* ITCH_SPI_CS */ /* GPP_D0 */
/* ITCH_SPI_CLK */ /* GPP_D1 */
/* ITCH_SPI_MISO_1 */ /* GPP_D2 */
/* ITCH_SPI_MISO_0 */ /* GPP_D3 */
/* CAM_FLASH_STROBE */ PAD_CFG_NF(GPP_D4, NONE, DEEP, NF1),
/* EN_PP3300_DX_EMMC */ PAD_CFG_GPO(GPP_D5, 1, DEEP),
/* EN_PP1800_DX_EMMC */ PAD_CFG_GPO(GPP_D6, 1, DEEP),
/* SH_I2C1_SDA */ PAD_CFG_NF(GPP_D7, NONE, DEEP, NF1),
/* SH_I2C1_SCL */ PAD_CFG_NF(GPP_D8, NONE, DEEP, NF1),
PAD_CFG_GPO(GPP_D9, 0, DEEP),
/* ITCH_SPI_CS */ PAD_CFG_NC(GPP_D0),
/* ITCH_SPI_CLK */ PAD_CFG_NC(GPP_D1),
/* ITCH_SPI_MISO_1 */ PAD_CFG_NC(GPP_D2),
/* ITCH_SPI_MISO_0 */ PAD_CFG_NC(GPP_D3),
/* CAM_FLASH_STROBE */ PAD_CFG_NC(GPP_D4),
/* EN_PP3300_DX_EMMC */ PAD_CFG_NC(GPP_D5),
/* EN_PP1800_DX_EMMC */ PAD_CFG_NC(GPP_D6),
/* SH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
/* SH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
/* ISH_SPI_CSB */ PAD_CFG_NC(GPP_D9),
/* USB_A0_ILIM_SEL */ PAD_CFG_GPO(GPP_D10, 1, DEEP),
/* USB_A1_ILIM_SEL */ PAD_CFG_GPO(GPP_D11, 1, DEEP),
/* EN_PP3300_DX_CAM */ PAD_CFG_GPO(GPP_D12, 1, DEEP),
/* EN_PP1800_DX_AUDIO */PAD_CFG_GPO(GPP_D13, 1, DEEP),
/* ISH_UART0_TXD */ /* GPP_D14 */
/* ISH_UART0_RTS */ /* GPP_D15 */
/* ISH_UART0_CTS */ /* GPP_D16 */
/* EN_PP3300_DX_CAM */ PAD_CFG_NC(GPP_D12),
/* EN_PP1800_DX_AUDIO */PAD_CFG_NC(GPP_D13),
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
/* ISH_UART0_RTS */ PAD_CFG_NC(GPP_D15),
/* ISH_UART0_CTS */ PAD_CFG_NC(GPP_D16),
/* DMIC_CLK_1 */ PAD_CFG_NF(GPP_D17, NONE, DEEP, NF1),
/* DMIC_DATA_1 */ PAD_CFG_NF(GPP_D18, NONE, DEEP, NF1),
/* DMIC_CLK_0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
/* DMIC_DATA_0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
/* ITCH_SPI_D2 */ /* GPP_D21 */
/* ITCH_SPI_D3 */ /* GPP_D22 */
/* ITCH_SPI_D2 */ PAD_CFG_NC(GPP_D21),
/* ITCH_SPI_D3 */ PAD_CFG_NC(GPP_D22),
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
/* SPI_TPM_IRQ */ PAD_CFG_GPI_APIC(GPP_E0, NONE, DEEP),
/* SATAXPCIE1 */ /* GPP_E1 */
/* SSD_PEDET */ PAD_CFG_GPI(GPP_E2, NONE, DEEP),
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
/* SSD_PEDET */ PAD_CFG_NC(GPP_E2),
/* AUDIO_DB_ID */ PAD_CFG_GPI(GPP_E3, NONE, DEEP),
/* SSD_SATA_DEVSLP */ PAD_CFG_GPO(GPP_E4, 0, DEEP),
/* SATA_DEVSLP1 */ /* GPP_E5 */
/* SATA_DEVSLP2 */ /* GPP_E6 */
/* SSD_SATA_DEVSLP */ PAD_CFG_NC(GPP_E4),
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
/* TCH_PNL_INTR* */ PAD_CFG_GPI_APIC(GPP_E7, NONE, DEEP),
/* SATALED# */ /* GPP_E8 */
/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* SATALED# */ PAD_CFG_NC(GPP_E8),
/* USB2_OC_0 */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1),
/* USB2_OC_1 */ PAD_CFG_NF(GPP_E10, NONE, DEEP, NF1),
/* USB2_OC_2 */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1),
/* USB2_OC_3 */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1),
/* DDI1_HPD */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
/* DDI2_HPD */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
/* EC_SMI */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
/* EC_SCI */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NF(GPP_E18, NONE, DEEP, NF1),
/* DDPB_CTRLCLK */ PAD_CFG_NC(GPP_E18),
/* DDPB_CTRLDATA */ PAD_CFG_NF(GPP_E19, NONE, DEEP, NF1),
/* DDPC_CTRLCLK */ PAD_CFG_NF(GPP_E20, NONE, DEEP, NF1),
/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
/* DDPC_CTRLDATA */ PAD_CFG_NF(GPP_E21, NONE, DEEP, NF1),
/* DDPD_CTRLCLK */ PAD_CFG_GPI(GPP_E22, NONE, DEEP),
/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
/* TCH_PNL_RST */ PAD_CFG_GPO(GPP_E23, 1, DEEP),
/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
/* I2C2_SDA */ /* GPP_F4 */
/* I2C2_SCL */ /* GPP_F5 */
/* I2C3_SDA */ /* GPP_F6 */
/* I2C3_SCL */ /* GPP_F7 */
/* I2S2_SCLK */ PAD_CFG_NC(GPP_F0),
/* I2S2_SFRM */ PAD_CFG_NC(GPP_F1),
/* I2S2_TXD */ PAD_CFG_NC(GPP_F2),
/* I2S2_RXD */ PAD_CFG_NC(GPP_F3),
/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
/* I2C4_SDA */ PAD_CFG_NF(GPP_F8, NONE, DEEP, NF1),
/* I2C4_SDA */ PAD_CFG_NF(GPP_F9, NONE, DEEP, NF1),
/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
/* AUDIO_IRQ */ PAD_CFG_GPI_APIC(GPP_F10, NONE, DEEP),
/* AUDIO_IRQ */ PAD_CFG_GPI_ACPI_SCI(GPP_F11, NONE, DEEP, YES),
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
@ -220,11 +220,11 @@ static const struct pad_config gpio_table[] = {
/* PM_SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
/* PM_SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
/* PM_SLP_SA# */ PAD_CFG_NF(GPD6, NONE, DEEP, NF1),
/* GPD7 */
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* PCH_SLP_WLAN# */ /* GPD9 */
/* PM_SLP_S5# */ PAD_CFG_NF(GPD10, NONE, DEEP, NF1),
/* LANPHYC */ /* GPD11 */
/* GPD7 */ PAD_CFG_NC(GPD7),
/* PM_SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
/* PCH_SLP_WLAN# */ PAD_CFG_NC(GPD9),
/* PM_SLP_S5# */ PAD_CFG_NC(GPD10),
/* LANPHYC */ PAD_CFG_NC(GPD11),
};
/* Early pad configuration in romstage. */