From 03c0853f4d58c73a632f81cac2eb16b759d7f338 Mon Sep 17 00:00:00 2001 From: Wisley Chen Date: Thu, 17 Feb 2022 15:53:06 +0600 Subject: [PATCH] mb/google/brya/redrix{4es}: Disable unused USB2/TCSS ports Disable unused USB2/TCSS Ports. BUG=b:217238553 TEST=FW_NAME=redrix emerge-brya coreboot Change-Id: I1cdee5b6dc56accb52ba1bf636bdf753a7bfd199 Signed-off-by: Wisley Chen Reviewed-on: https://review.coreboot.org/c/coreboot/+/62069 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/brya/variants/redrix/overridetree.cb | 5 +++++ src/mainboard/google/brya/variants/redrix4es/overridetree.cb | 5 +++++ 2 files changed, 10 insertions(+) diff --git a/src/mainboard/google/brya/variants/redrix/overridetree.cb b/src/mainboard/google/brya/variants/redrix/overridetree.cb index af7f752ad3..62a24eda68 100644 --- a/src/mainboard/google/brya/variants/redrix/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix/overridetree.cb @@ -41,6 +41,11 @@ chip soc/intel/alderlake register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value | diff --git a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb index 22a9883374..5cb105df65 100644 --- a/src/mainboard/google/brya/variants/redrix4es/overridetree.cb +++ b/src/mainboard/google/brya/variants/redrix4es/overridetree.cb @@ -41,6 +41,11 @@ chip soc/intel/alderlake register "SlowSlewRate[VR_DOMAIN_IA]" = "SLEW_FAST_8" register "FastPkgCRampDisable[VR_DOMAIN_IA]" = "1" + register "usb2_ports[1]" = "USB2_PORT_EMPTY" + register "usb2_ports[5]" = "USB2_PORT_EMPTY" + register "usb2_ports[9]" = "USB2_PORT_EMPTY" + register "tcss_ports[1]" = "TCSS_PORT_EMPTY" + # Intel Common SoC Config #+-------------------+---------------------------+ #| Field | Value |