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mb/google/brya/var/gimble: Improve USB2 eye diagram of DB Type-C port 

- Set MAX OC1 to USB2_C1

BUG=b:205676803
TEST=USE="project_gimble emerge-brya coreboot" and verify it builds
without error.

Signed-off-by: Mark Hsieh <mark_hsieh@wistron.corp-partner.google.com>
Change-Id: Idcf13ad072ae5d7a897f54adb19e6b2b068609dc
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Zhuohao Lee <zhuohao@google.com>
This commit is contained in:
Mark Hsieh 2021-11-10 20:58:49 +08:00 committed by Paul Fagerburg
parent 5164e4b03f
commit 03c3d5d68e
1 changed files with 1 additions and 0 deletions
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src/mainboard/google/brya/variants/gimble/overridetree.cb
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@ -34,6 +34,7 @@ chip soc/intel/alderlake
register "SaGv" = "SaGv_Enabled"
register "TcssAuxOri" = "1"
register "typec_aux_bias_pads[0]" = "{.pad_auxp_dc = GPP_E22, .pad_auxn_dc = GPP_E23}"
register "usb2_ports[1]" = "USB2_PORT_MAX(OC1)" # set MAX to USB2_C1 for eye diagram
register "usb2_ports[2]" = "USB2_PORT_EMPTY" # Disable USB2_C2
register "usb2_ports[3]" = "USB2_PORT_EMPTY" # M.2 WWAN
register "usb2_ports[7]" = "USB2_PORT_MID(OC_SKIP)" # Type-A MLB Port