From 03e44f46b080022a0c8949b2cc7ba88d587e671e Mon Sep 17 00:00:00 2001 From: Lijian Zhao Date: Tue, 25 Jul 2017 18:42:29 -0700 Subject: [PATCH] soc/intel/cannonlake: Correct gpio definition The following changes have been applied for GPIO: 1. Correct port id using by GPIO community 3 for CNL-LP. 2. Correct number of doubleword for each pad from 2 to 4. Change-Id: I717d1ffba8e6722543f4cf8083fe6145fa85e184 Signed-off-by: Lijian Zhao Reviewed-on: https://review.coreboot.org/20775 Tested-by: build bot (Jenkins) Reviewed-by: Aaron Durbin Reviewed-by: Paul Menzel --- src/soc/intel/cannonlake/gpio.c | 2 +- src/soc/intel/cannonlake/include/soc/gpio_defs.h | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/src/soc/intel/cannonlake/gpio.c b/src/soc/intel/cannonlake/gpio.c index 2dd90f9f01..68b137d742 100644 --- a/src/soc/intel/cannonlake/gpio.c +++ b/src/soc/intel/cannonlake/gpio.c @@ -75,7 +75,7 @@ static const struct pad_community cnl_communities[] = { .reset_map = rst_map, .num_reset_vals = ARRAY_SIZE(rst_map), }, { /* GPP C, E */ - .port = PID_GPIOCOM3, + .port = PID_GPIOCOM4, .first_pad = GPP_C0, .last_pad = GPP_E23, .num_gpi_regs = NUM_GPIO_COM3_GPI_REGS, diff --git a/src/soc/intel/cannonlake/include/soc/gpio_defs.h b/src/soc/intel/cannonlake/include/soc/gpio_defs.h index 46ab1d98c6..6e84f838f1 100644 --- a/src/soc/intel/cannonlake/include/soc/gpio_defs.h +++ b/src/soc/intel/cannonlake/include/soc/gpio_defs.h @@ -22,7 +22,7 @@ #include -#define GPIO_NUM_PAD_CFG_REGS 2 /* DW0, DW1 */ +#define GPIO_NUM_PAD_CFG_REGS 4 /* DW0, DW1, DW2, DW3 */ #define NUM_GPIO_COMx_GPI_REGS(n) \ (ALIGN_UP((n), GPIO_MAX_NUM_PER_GROUP) / GPIO_MAX_NUM_PER_GROUP)