GNUBoot
/
coreboot-kgpe-d16
2
0
Fork 0
Code Issues Pull Requests Packages Projects Releases Wiki Activity

amd/pi/hudson: Move APIC enable to CPU file 

Relocate the enabling of the LAPIC out of the southbridge source and
surround it with a check for CONFIG_UDELAY_LAPIC (typical for AMD
systems).  The LAPIC is now enabled for all cores; not only the BSP,
and not only when the UART is used.

This solves the problem of APs not having their APICs enabled when
the timer is expected to be functional, e.g. verstage often uses
do_printk_va_list() instead of do_printk() which exits early for
APs when CONFIG_SQUELCH_EARLY_SMP=y.

The changes were tested with two Gardenia builds, one using verstage
and another with CONFIG_SQUELCH_EARLY_SMP=n.

Original-Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Original-Reviewed-by: Marc Jones <marcj303@gmail.com>
(cherry picked from commit 93ffc311165f19d4192a5489051fa4264cd8e0ad)

Change-Id: Ieaecc0bf921ee0d2691a8082f2431ea4d0c33749
Signed-off-by: Marc Jones <marcj303@gmail.com>
Signed-off-by: Marshall Dawson <marshalldawson3rd@gmail.com>
Reviewed-on: https://review.coreboot.org/18436
Tested-by: build bot (Jenkins)
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
This commit is contained in:
Marshall Dawson 2017-02-12 10:31:15 -07:00 committed by Marc Jones
parent a0891ee367
commit 03e6a455a3
5 changed files with 24 additions and 4 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

6
src/cpu/amd/pi/00630F01/fixme.c
View File

@ -77,4 +77,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
} }

6
src/cpu/amd/pi/00660F01/fixme.c
View File

@ -84,4 +84,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
} }

6
src/cpu/amd/pi/00670F00/fixme.c
View File

@ -88,4 +88,10 @@ void amd_initmmio(void)
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \ MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | \
0x800ull; 0x800ull;
LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite(0x20D, &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
} }

6
src/cpu/amd/pi/00730F01/fixme.c
View File

@ -89,4 +89,10 @@ void amd_initmmio(void)
LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20C, &MsrReg, &StdHeader);
MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull; MsrReg = ((1ULL << CONFIG_CPU_ADDR_BITS) - CACHE_ROM_SIZE) | 0x800ull;
LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader); LibAmdMsrWrite (0x20D, &MsrReg, &StdHeader);
if (IS_ENABLED(CONFIG_UDELAY_LAPIC)){
LibAmdMsrRead(0x1B, &MsrReg, &StdHeader);
MsrReg |= 1 << 11;
LibAmdMsrWrite(0x1B, &MsrReg, &StdHeader);
}
} }

4
src/southbridge/amd/pi/hudson/early_setup.c
View File

@ -34,12 +34,8 @@
void configure_hudson_uart(void) void configure_hudson_uart(void)
{ {
msr_t msr;
u8 byte; u8 byte;
msr = rdmsr(0x1B);
msr.lo |= 1 << 11;
wrmsr(0x1B, msr);
byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2); byte = read8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2);
byte |= 1 << 3; byte |= 1 << 3;
write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte); write8((void *)ACPI_MMIO_BASE + AOAC_BASE + FCH_AOAC_REG56 + CONFIG_UART_FOR_CONSOLE * 2, byte);