soc/intel/cannonlake: Move tco_configure to bootblock

Similar to CB:43313 (SHA bb50c67227), it seems possible for the same
problem to come up on cannonlake. Again, it should be harmless to
configure the TCO device earlier in the boot flow.

Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Change-Id: Ib8883d27b2a0994a67ec5e044a692a2e853fd680
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43538
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>

src/soc/intel/cannonlake/bootblock/bootblock.c

@@ -3,6 +3,7 @@
 #include <bootblock_common.h>
 #include <cpu/x86/mtrr.h>
 #include <intelblocks/gspi.h>
+#include <intelblocks/tco.h>
 #include <intelblocks/uart.h>
 #include <soc/bootblock.h>
 #include <soc/iomap.h>
@@ -65,4 +66,7 @@ void bootblock_soc_init(void)
 	gpi_clear_int_cfg();
 	report_platform_info();
 	bootblock_pch_init();
+
+	/* Program TCO_BASE_ADDRESS and TCO Timer Halt */
+	tco_configure();
 }

src/soc/intel/cannonlake/romstage/pch.c

@@ -1,14 +1,10 @@
 /* SPDX-License-Identifier: GPL-2.0-only */
 
 #include <intelblocks/smbus.h>
-#include <intelblocks/tco.h>
 #include <soc/romstage.h>
 
 void romstage_pch_init(void)
 {
-	/* Program TCO_BASE_ADDRESS and TCO Timer Halt */
-	tco_configure();
-
 	/* Program SMBUS_BASE_ADDRESS and enable it */
 	smbus_common_init();
 }