vendorcode/intel/fsp: Add Jasper Lake FSP headers for FSP v1433
The FSP-M/S/T headers added are generated as per FSP v1433. Change-Id: Iacb44204c3f7220a20ab3edc2163c97188014bbf Signed-off-by: Aamir Bohra <aamir.bohra@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/37559 Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com> Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Aamir Bohra
Subrata Banik
parent
bf14c0050c
commit
03f78b069d
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/** @file
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Header file for Firmware Version Information
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@copyright
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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This program and the accompanying materials are licensed and made available under
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the terms and conditions of the BSD License which accompanies this distribution.
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The full text of the license may be found at
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http://opensource.org/licenses/bsd-license.php
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THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
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WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
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**/
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#ifndef _FIRMWARE_VERSION_INFO_HOB_H_
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#define _FIRMWARE_VERSION_INFO_HOB_H_
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#include <Uefi/UefiMultiPhase.h>
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#include <Pi/PiBootMode.h>
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#include <Pi/PiHob.h>
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#pragma pack(1)
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///
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/// Firmware Version Structure
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///
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typedef struct {
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UINT8 MajorVersion;
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UINT8 MinorVersion;
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UINT8 Revision;
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UINT16 BuildNumber;
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} FIRMWARE_VERSION;
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///
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/// Firmware Version Information Structure
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///
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typedef struct {
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UINT8 ComponentNameIndex; ///< Offset 0 Index of Component Name
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UINT8 VersionStringIndex; ///< Offset 1 Index of Version String
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FIRMWARE_VERSION Version; ///< Offset 2-6 Firmware version
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} FIRMWARE_VERSION_INFO;
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#ifndef __SMBIOS_STANDARD_H__
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///
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/// The Smbios structure header.
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///
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typedef struct {
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UINT8 Type;
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UINT8 Length;
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UINT16 Handle;
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} SMBIOS_STRUCTURE;
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#endif
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///
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/// Firmware Version Information HOB Structure
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///
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typedef struct {
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EFI_HOB_GUID_TYPE Header; ///< Offset 0-23 The header of FVI HOB
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SMBIOS_STRUCTURE SmbiosData; ///< Offset 24-27 The SMBIOS header of FVI HOB
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UINT8 Count; ///< Offset 28 Number of FVI elements included.
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///
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/// FIRMWARE_VERSION_INFO structures followed by the null terminated string buffer
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///
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} FIRMWARE_VERSION_INFO_HOB;
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#pragma pack()
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#endif // _FIRMWARE_VERSION_INFO_HOB_H_
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/** @file
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPUPD_H__
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#define __FSPUPD_H__
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#include <FspEas.h>
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#pragma pack(1)
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#define FSPT_UPD_SIGNATURE 0x545F4450554C534A /* 'JSLUPD_T' */
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#define FSPM_UPD_SIGNATURE 0x4D5F4450554C534A /* 'JSLUPD_M' */
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#define FSPS_UPD_SIGNATURE 0x535F4450554C534A /* 'JSLUPD_S' */
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#pragma pack()
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#endif
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/** @file
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Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
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Redistribution and use in source and binary forms, with or without modification,
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are permitted provided that the following conditions are met:
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* Redistributions of source code must retain the above copyright notice, this
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list of conditions and the following disclaimer.
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* Redistributions in binary form must reproduce the above copyright notice, this
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list of conditions and the following disclaimer in the documentation and/or
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other materials provided with the distribution.
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* Neither the name of Intel Corporation nor the names of its contributors may
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be used to endorse or promote products derived from this software without
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specific prior written permission.
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THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
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AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
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IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
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ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
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LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
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CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
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SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
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INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
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CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
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ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
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THE POSSIBILITY OF SUCH DAMAGE.
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This file is automatically generated. Please do NOT modify !!!
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**/
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#ifndef __FSPMUPD_H__
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#define __FSPMUPD_H__
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#include <FspUpd.h>
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#pragma pack(1)
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#include <MemInfoHob.h>
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///
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/// The ChipsetInit Info structure provides the information of ME ChipsetInit CRC and BIOS ChipsetInit CRC.
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///
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typedef struct {
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UINT8 Revision; ///< Chipset Init Info Revision
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UINT8 Rsvd[3]; ///< Reserved
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UINT16 MeChipInitCrc; ///< 16 bit CRC value of MeChipInit Table
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UINT16 BiosChipInitCrc; ///< 16 bit CRC value of PchChipInit Table
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} CHIPSET_INIT_INFO;
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/** Fsp M Configuration
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**/
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typedef struct {
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/** Offset 0x0040 - Reserved
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**/
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UINT8 Reserved0[8];
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/** Offset 0x0048 - SPD Data Length
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Length of SPD Data
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0x100:256 Bytes, 0x200:512 Bytes
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**/
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UINT16 MemorySpdDataLen;
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/** Offset 0x004A - Reserved
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**/
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UINT8 Reserved1[2];
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/** Offset 0x004C - Memory SPD Pointer Channel 0 Dimm 0
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Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
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**/
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UINT32 MemorySpdPtr00;
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/** Offset 0x0050 - Reserved
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**/
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UINT8 Reserved2[4];
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/** Offset 0x0054 - Memory SPD Pointer Channel 1 Dimm 0
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Pointer to SPD data, will be used only when SpdAddressTable SPD Address are marked as 00
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**/
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UINT32 MemorySpdPtr10;
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/** Offset 0x0058 - Reserved
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**/
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UINT8 Reserved3[4];
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/** Offset 0x005C - Dq Byte Map CH0
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Dq byte mapping between CPU and DRAM, Channel 0: board-dependent
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**/
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UINT8 DqByteMapCh0[12];
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/** Offset 0x0068 - Dq Byte Map CH1
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Dq byte mapping between CPU and DRAM, Channel 1: board-dependent
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**/
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UINT8 DqByteMapCh1[12];
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/** Offset 0x0074 - Dqs Map CPU to DRAM CH 0
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Set Dqs mapping relationship between CPU and DRAM, Channel 0: board-dependent
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**/
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UINT8 DqsMapCpu2DramCh0[8];
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/** Offset 0x007C - Dqs Map CPU to DRAM CH 1
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Set Dqs mapping relationship between CPU and DRAM, Channel 1: board-dependent
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**/
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UINT8 DqsMapCpu2DramCh1[8];
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/** Offset 0x0084 - RcompResister settings
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Indicates RcompReister settings: Board-dependent
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**/
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UINT16 RcompResistor[3];
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/** Offset 0x008A - RcompTarget settings
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RcompTarget settings: board-dependent
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**/
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UINT16 RcompTarget[5];
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/** Offset 0x0094 - Dqs Pins Interleaved Setting
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Indicates DqPinsInterleaved setting: board-dependent
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$EN_DIS
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**/
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UINT8 DqPinsInterleaved;
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/** Offset 0x0095 - VREF_CA
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CA Vref routing: board-dependent
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0:VREF_CA goes to both CH_A and CH_B, 1: VREF_CA to CH_A and VREF_DQ_A to CH_B,
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2:VREF_CA to CH_A and VREF_DQ_B to CH_B
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**/
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UINT8 CaVrefConfig;
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/** Offset 0x0096 - Reserved
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**/
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UINT8 Reserved4[6];
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/** Offset 0x009C - Intel Enhanced Debug
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Intel Enhanced Debug (IED): 0=Disabled, 0x400000=Enabled and 4MB SMRAM occupied
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0 : Disable, 0x400000 : Enable
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**/
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UINT32 IedSize;
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/** Offset 0x00A0 - Tseg Size
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Size of SMRAM memory reserved. 0x400000 for Release build and 0x1000000 for Debug build
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0x0400000:4MB, 0x01000000:16MB
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**/
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UINT32 TsegSize;
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/** Offset 0x00A4 - Reserved
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**/
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UINT8 Reserved5[6];
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/** Offset 0x00AA - Enable SMBus
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Enable/disable SMBus controller.
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$EN_DIS
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**/
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UINT8 SmbusEnable;
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/** Offset 0x00AB - Spd Address Tabl
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Specify SPD Address table for CH0D0/CH0D1/CH1D0&CH1D1. MemorySpdPtr will be used
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if SPD Address is 00
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**/
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UINT8 SpdAddressTable[4];
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/** Offset 0x00AF - Platform Debug Consent
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To 'opt-in' for debug, please select 'Enabled' with the desired debug probe type.
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Enabling this BIOS option may alter the default value of other debug-related BIOS
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options.\Manual: Do not use Platform Debug Consent to override other debug-relevant
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policies, but the user must set each debug option manually, aimed at advanced users.\n
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Note: DCI OOB (aka BSSB) uses CCA probe.
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0:Disabled, 2:Enabled (DCI OOB), 3:Enabled (USB3 DbC), 4:Enabled (XDP/MIPI60), 5:Enabled
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(USB2 DbC), 6:Enable (2-wire DCI OOB), 7:Manual
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**/
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UINT8 PlatformDebugConsent;
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/** Offset 0x00B0 - Reserved
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**/
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UINT8 Reserved6[2];
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/** Offset 0x00B2 - Enable DCI ModPHY Pwoer Gate
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Enable ModPHY Pwoer Gate when DCI is enabled
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$EN_DIS
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**/
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UINT8 DciModphyPg;
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/** Offset 0x00B3 - Reserved
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**/
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UINT8 Reserved7;
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/** Offset 0x00B4 - PCH Trace Hub Mode
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Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
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if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
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0: Disable, 1: Target Debugger Mode, 2: Host Debugger Mode
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**/
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UINT8 PchTraceHubMode;
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/** Offset 0x00B5 - Reserved
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**/
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UINT8 Reserved8[47];
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/** Offset 0x00E4 - Disable VT-d
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0=Enable/FALSE(VT-d enabled), 1=Disable/TRUE (VT-d disabled)
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$EN_DIS
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**/
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UINT8 VtdDisable;
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/** Offset 0x00E5 - Reserved
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**/
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UINT8 Reserved9[3];
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/** Offset 0x00E8 - Internal Graphics Pre-allocated Memory
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Size of memory preallocated for internal graphics.
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0x00:0MB, 0x01:32MB, 0x02:64MB, 0x03:96MB, 0x04:128MB, 0x05:160MB, 0xF0:4MB, 0xF1:8MB,
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0xF2:12MB, 0xF3:16MB, 0xF4:20MB, 0xF5:24MB, 0xF6:28MB, 0xF7:32MB, 0xF8:36MB, 0xF9:40MB,
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0xFA:44MB, 0xFB:48MB, 0xFC:52MB, 0xFD:56MB, 0xFE:60MB
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**/
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UINT8 IgdDvmt50PreAlloc;
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/** Offset 0x00E9 - Internal Graphics
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Enable/disable internal graphics.
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$EN_DIS
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**/
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UINT8 InternalGfx;
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/** Offset 0x00EA - Reserved
|
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**/
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UINT8 Reserved10;
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|
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/** Offset 0x00EB - Board Type
|
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MrcBoardType, Options are 0=Mobile/Mobile Halo, 1=Desktop/DT Halo, 5=ULT/ULX/Mobile
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Halo, 7=UP Server
|
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0:Mobile/Mobile Halo, 1:Desktop/DT Halo, 5:ULT/ULX/Mobile Halo, 7:UP Server
|
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**/
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UINT8 UserBd;
|
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/** Offset 0x00EC - Reserved
|
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**/
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UINT8 Reserved11[2];
|
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|
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/** Offset 0x00EE - SA GV
|
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System Agent dynamic frequency support and when enabled memory will be training
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at three different frequencies.
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0:Disabled, 1:FixedLow, 2:FixedMid, 3:FixedHigh, 4:Enabled
|
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**/
|
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UINT8 SaGv;
|
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|
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/** Offset 0x00EF - Reserved
|
||||
**/
|
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UINT8 Reserved12[5];
|
||||
|
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/** Offset 0x00F4 - Rank Margin Tool
|
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Enable/disable Rank Margin Tool.
|
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$EN_DIS
|
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**/
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UINT8 RMT;
|
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|
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/** Offset 0x00F5 - Reserved
|
||||
**/
|
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UINT8 Reserved13[24];
|
||||
|
||||
/** Offset 0x010D - Memory Reference Clock
|
||||
100MHz, 133MHz.
|
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0:133MHz, 1:100MHz
|
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**/
|
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UINT8 RefClk;
|
||||
|
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/** Offset 0x010E - Reserved
|
||||
**/
|
||||
UINT8 Reserved14[26];
|
||||
|
||||
/** Offset 0x0128 - Enable Intel HD Audio (Azalia)
|
||||
0: Disable, 1: Enable (Default) Azalia controller
|
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$EN_DIS
|
||||
**/
|
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UINT8 PchHdaEnable;
|
||||
|
||||
/** Offset 0x0129 - CPU Trace Hub Mode
|
||||
Select 'Host Debugger' if Trace Hub is used with host debugger tool or 'Target Debugger'
|
||||
if Trace Hub is used by target debugger software or 'Disable' trace hub functionality.
|
||||
0: Disable, 1:Target Debugger Mode, 2:Host Debugger Mode
|
||||
**/
|
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UINT8 CpuTraceHubMode;
|
||||
|
||||
/** Offset 0x012A - Reserved
|
||||
**/
|
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UINT8 Reserved15[98];
|
||||
|
||||
/** Offset 0x018C - Program GPIOs for LFP on DDI port-A device
|
||||
0=Disabled,1(Default)=eDP, 2=MIPI DSI
|
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0:Disabled, 1:eDP, 2:MIPI DSI
|
||||
**/
|
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UINT8 DdiPortAConfig;
|
||||
|
||||
/** Offset 0x018D - Reserved
|
||||
**/
|
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UINT8 Reserved16[2];
|
||||
|
||||
/** Offset 0x018F - Enable or disable HPD of DDI port B
|
||||
0=Disable, 1(Default)=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortBHpd;
|
||||
|
||||
/** Offset 0x0190 - Enable or disable HPD of DDI port C
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortCHpd;
|
||||
|
||||
/** Offset 0x0191 - Reserved
|
||||
**/
|
||||
UINT8 Reserved17[5];
|
||||
|
||||
/** Offset 0x0196 - Enable or disable DDC of DDI port B
|
||||
0=Disable, 1(Default)=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortBDdc;
|
||||
|
||||
/** Offset 0x0197 - Enable or disable DDC of DDI port C
|
||||
0(Default)=Disable, 1=Enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DdiPortCDdc;
|
||||
|
||||
/** Offset 0x0198 - Reserved
|
||||
**/
|
||||
UINT8 Reserved18[165];
|
||||
|
||||
/** Offset 0x023D - C6DRAM power gating feature
|
||||
This policy indicates whether or not BIOS should allocate PRMRR memory for C6DRAM
|
||||
power gating feature.- 0: Don't allocate any PRMRR memory for C6DRAM power gating
|
||||
feature.- <b>1: Allocate PRMRR memory for C6DRAM power gating feature</b>.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 EnableC6Dram;
|
||||
|
||||
/** Offset 0x023E - Reserved
|
||||
**/
|
||||
UINT8 Reserved19[7];
|
||||
|
||||
/** Offset 0x0245 - CPU ratio value
|
||||
CPU ratio value. Valid Range 0 to 63
|
||||
**/
|
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UINT8 CpuRatio;
|
||||
|
||||
/** Offset 0x0246 - Reserved
|
||||
**/
|
||||
UINT8 Reserved20[4];
|
||||
|
||||
/** Offset 0x024A - Enable or Disable VMX
|
||||
Enable or Disable VMX; 0: Disable; <b>1: Enable</b>.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 VmxEnable;
|
||||
|
||||
/** Offset 0x024B - Reserved
|
||||
**/
|
||||
UINT8 Reserved21[31];
|
||||
|
||||
/** Offset 0x026A - BiosGuard
|
||||
Enable/Disable. 0: Disable, Enable/Disable BIOS Guard feature, 1: enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 BiosGuard;
|
||||
|
||||
/** Offset 0x026B - Reserved
|
||||
**/
|
||||
UINT8 Reserved22[5];
|
||||
|
||||
/** Offset 0x0270 - PrmrrSize
|
||||
Enable/Disable. 0: Disable, define default value of PrmrrSize , 1: enable
|
||||
**/
|
||||
UINT32 PrmrrSize;
|
||||
|
||||
/** Offset 0x0274 - SinitMemorySize
|
||||
Enable/Disable. 0: Disable, define default value of SinitMemorySize , 1: enable
|
||||
**/
|
||||
UINT32 SinitMemorySize;
|
||||
|
||||
/** Offset 0x0278 - Reserved
|
||||
**/
|
||||
UINT8 Reserved23[543];
|
||||
|
||||
/** Offset 0x0497 - Usage type for ClkSrc
|
||||
0-23: PCH rootport, 0x40-0x43: PEG port, 0x70:LAN, 0x80: unspecified but in use
|
||||
(free running), 0xFF: not used
|
||||
**/
|
||||
UINT8 PcieClkSrcUsage[16];
|
||||
|
||||
/** Offset 0x04A7 - ClkReq-to-ClkSrc mapping
|
||||
Number of ClkReq signal assigned to ClkSrc
|
||||
**/
|
||||
UINT8 PcieClkSrcClkReq[16];
|
||||
|
||||
/** Offset 0x04B7 - Reserved
|
||||
**/
|
||||
UINT8 Reserved24[5];
|
||||
|
||||
/** Offset 0x04BC - Enable PCIE RP Mask
|
||||
Enable/disable PCIE Root Ports. 0: disable, 1: enable. One bit for each port, bit0
|
||||
for port1, bit1 for port2, and so on.
|
||||
**/
|
||||
UINT32 PcieRpEnableMask;
|
||||
|
||||
/** Offset 0x04C0 - Debug Interfaces
|
||||
Debug Interfaces. BIT0-RAM, BIT1-UART, BIT3-USB3, BIT4-Serial IO, BIT5-TraceHub,
|
||||
BIT2 - Not used.
|
||||
**/
|
||||
UINT8 PcdDebugInterfaceFlags;
|
||||
|
||||
/** Offset 0x04C1 - Serial Io Uart Debug Controller Number
|
||||
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
|
||||
Core interface, it cannot be used for debug purpose.
|
||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 SerialIoUartDebugControllerNumber;
|
||||
|
||||
/** Offset 0x04C2 - Reserved
|
||||
**/
|
||||
UINT8 Reserved25[22];
|
||||
|
||||
/** Offset 0x04D8 - Early Command Training
|
||||
Enables/Disable Early Command Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 ECT;
|
||||
|
||||
/** Offset 0x04D9 - Reserved
|
||||
**/
|
||||
UINT8 Reserved26[2];
|
||||
|
||||
/** Offset 0x04DB - Read MPR Training
|
||||
Enables/Disable Read MPR Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RDMPRT;
|
||||
|
||||
/** Offset 0x04DC - Reserved
|
||||
**/
|
||||
UINT8 Reserved27[7];
|
||||
|
||||
/** Offset 0x04E3 - Dimm ODT Training
|
||||
Enables/Disable Dimm ODT Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DIMMODTT;
|
||||
|
||||
/** Offset 0x04E4 - DIMM RON Training
|
||||
Enables/Disable DIMM RON Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 DIMMRONT;
|
||||
|
||||
/** Offset 0x04E5 - Reserved
|
||||
**/
|
||||
UINT8 Reserved28;
|
||||
|
||||
/** Offset 0x04E6 - Write Slew Rate Training
|
||||
Enables/Disable Write Slew Rate Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 WRSRT;
|
||||
|
||||
/** Offset 0x04E7 - Read ODT Training
|
||||
Enables/Disable Read ODT Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RDODTT;
|
||||
|
||||
/** Offset 0x04E8 - Read Equalization Training
|
||||
Enables/Disable Read Equalization Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RDEQT;
|
||||
|
||||
/** Offset 0x04E9 - Read Amplifier Training
|
||||
Enables/Disable Read Amplifier Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RDAPT;
|
||||
|
||||
/** Offset 0x04EA - Reserved
|
||||
**/
|
||||
UINT8 Reserved29[3];
|
||||
|
||||
/** Offset 0x04ED - Read Voltage Centering 2D
|
||||
Enables/Disable Read Voltage Centering 2D
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RDVC2D;
|
||||
|
||||
/** Offset 0x04EE - Reserved
|
||||
**/
|
||||
UINT8 Reserved30[3];
|
||||
|
||||
/** Offset 0x04F1 - Turn Around Timing Training
|
||||
Enables/Disable Turn Around Timing Training
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 TAT;
|
||||
|
||||
/** Offset 0x04F2 - Reserved
|
||||
**/
|
||||
UINT8 Reserved31[6];
|
||||
|
||||
/** Offset 0x04F8 - Receive Enable Centering 1D
|
||||
Enables/Disable Receive Enable Centering 1D
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RCVENC1D;
|
||||
|
||||
/** Offset 0x04F9 - Retrain Margin Check
|
||||
Enables/Disable Retrain Margin Check
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RMC;
|
||||
|
||||
/** Offset 0x04FA - Reserved
|
||||
**/
|
||||
UINT8 Reserved32[60];
|
||||
|
||||
/** Offset 0x0536 - RAPL PL 1 WindowX
|
||||
Power PL 1 time window X value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
|
||||
**/
|
||||
UINT8 RaplLim1WindX;
|
||||
|
||||
/** Offset 0x0537 - RAPL PL 1 WindowY
|
||||
Power PL 1 time window Y value, (1/1024)*(1+(x/4))*(2^y) (0=Def)
|
||||
**/
|
||||
UINT8 RaplLim1WindY;
|
||||
|
||||
/** Offset 0x0538 - Reserved
|
||||
**/
|
||||
UINT8 Reserved33[2];
|
||||
|
||||
/** Offset 0x053A - RAPL PL 1 Power
|
||||
range[0;2^14-1]= [2047.875;0]in W, (224= Def)
|
||||
**/
|
||||
UINT16 RaplLim1Pwr;
|
||||
|
||||
/** Offset 0x053C - Reserved
|
||||
**/
|
||||
UINT8 Reserved34[68];
|
||||
|
||||
/** Offset 0x0580 - LpDdrDqDqsReTraining
|
||||
Enables/Disable LpDdrDqDqsReTraining
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 LpDdrDqDqsReTraining;
|
||||
|
||||
/** Offset 0x0581 - Reserved
|
||||
**/
|
||||
UINT8 Reserved35[172];
|
||||
|
||||
/** Offset 0x062D - Enable HD Audio Link
|
||||
Enable/disable HD Audio Link. Muxed with SSP0/SSP1/SNDW1.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PchHdaAudioLinkHdaEnable;
|
||||
|
||||
/** Offset 0x062E - Reserved
|
||||
**/
|
||||
UINT8 Reserved36[3];
|
||||
|
||||
/** Offset 0x0631 - Enable HD Audio DMIC_N Link
|
||||
Enable/disable HD Audio DMIC1 link. Muxed with SNDW3.
|
||||
**/
|
||||
UINT8 PchHdaAudioLinkDmicEnable[2];
|
||||
|
||||
/** Offset 0x0633 - Reserved
|
||||
**/
|
||||
UINT8 Reserved37[17];
|
||||
|
||||
/** Offset 0x0644 - Enable HD Audio DSP
|
||||
Enable/disable HD Audio DSP feature.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PchHdaDspEnable;
|
||||
|
||||
/** Offset 0x0645 - Reserved
|
||||
**/
|
||||
UINT8 Reserved38[11];
|
||||
|
||||
/** Offset 0x0650 - Enable HD Audio SSP0 Link
|
||||
Enable/disable HD Audio SSP_N/I2S link. Muxed with HDA. N-number 0-5
|
||||
**/
|
||||
UINT8 PchHdaAudioLinkSspEnable[6];
|
||||
|
||||
/** Offset 0x0656 - Enable HD Audio SoundWire#N Link
|
||||
Enable/disable HD Audio SNDW#N link. Muxed with HDA.
|
||||
**/
|
||||
UINT8 PchHdaAudioLinkSndwEnable[4];
|
||||
|
||||
/** Offset 0x065A - Reserved
|
||||
**/
|
||||
UINT8 Reserved39[7];
|
||||
|
||||
/** Offset 0x0661 - Skip MBP HOB
|
||||
Test, 0: disable, 1: enable, Enable/Disable MOB HOB.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 SkipMbpHob;
|
||||
|
||||
/** Offset 0x0662 - Reserved
|
||||
**/
|
||||
UINT8 Reserved40[22];
|
||||
} FSP_M_CONFIG;
|
||||
|
||||
/** Fsp M UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPM_ARCH_UPD FspmArchUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSP_M_CONFIG FspmConfig;
|
||||
|
||||
/** Offset 0x0678
|
||||
**/
|
||||
UINT8 UnusedUpdSpace19[6];
|
||||
|
||||
/** Offset 0x067E
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPM_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,656 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPSUPD_H__
|
||||
#define __FSPSUPD_H__
|
||||
|
||||
#include <FspUpd.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
|
||||
///
|
||||
/// Azalia Header structure
|
||||
///
|
||||
typedef struct {
|
||||
UINT16 VendorId; ///< Codec Vendor ID
|
||||
UINT16 DeviceId; ///< Codec Device ID
|
||||
UINT8 RevisionId; ///< Revision ID of the codec. 0xFF matches any revision.
|
||||
UINT8 SdiNum; ///< SDI number, 0xFF matches any SDI.
|
||||
UINT16 DataDwords; ///< Number of data DWORDs pointed by the codec data buffer.
|
||||
UINT32 Reserved; ///< Reserved for future use. Must be set to 0.
|
||||
} AZALIA_HEADER;
|
||||
|
||||
///
|
||||
/// Audio Azalia Verb Table structure
|
||||
///
|
||||
typedef struct {
|
||||
AZALIA_HEADER Header; ///< AZALIA PCH header
|
||||
UINT32 *Data; ///< Pointer to the data buffer. Its length is specified in the header
|
||||
} AUDIO_AZALIA_VERB_TABLE;
|
||||
|
||||
///
|
||||
/// Refer to the definition of PCH_INT_PIN
|
||||
///
|
||||
typedef enum {
|
||||
SiPchNoInt, ///< No Interrupt Pin
|
||||
SiPchIntA,
|
||||
SiPchIntB,
|
||||
SiPchIntC,
|
||||
SiPchIntD
|
||||
} SI_PCH_INT_PIN;
|
||||
///
|
||||
/// The PCH_DEVICE_INTERRUPT_CONFIG block describes interrupt pin, IRQ and interrupt mode for PCH device.
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Device; ///< Device number
|
||||
UINT8 Function; ///< Device function
|
||||
UINT8 IntX; ///< Interrupt pin: INTA-INTD (see SI_PCH_INT_PIN)
|
||||
UINT8 Irq; ///< IRQ to be set for device.
|
||||
} SI_PCH_DEVICE_INTERRUPT_CONFIG;
|
||||
|
||||
#define SI_PCH_MAX_DEVICE_INTERRUPT_CONFIG 64 ///< Number of all PCH devices
|
||||
|
||||
|
||||
/** Fsp S Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0020 - Reserved
|
||||
**/
|
||||
UINT8 Reserved0[16];
|
||||
|
||||
/** Offset 0x0030 - Graphics Configuration Ptr
|
||||
Points to VBT
|
||||
**/
|
||||
UINT32 GraphicsConfigPtr;
|
||||
|
||||
/** Offset 0x0034 - Enable Device 4
|
||||
Enable/disable Device 4
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 Device4Enable;
|
||||
|
||||
/** Offset 0x0035 - Enable eMMC Controller
|
||||
Enable/disable eMMC Controller.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 ScsEmmcEnabled;
|
||||
|
||||
/** Offset 0x0036 - Enable eMMC HS400 Mode
|
||||
Enable eMMC HS400 Mode.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 ScsEmmcHs400Enabled;
|
||||
|
||||
/** Offset 0x0037 - Use DLL values from policy
|
||||
Set if FSP should use HS400 DLL values from policy
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 EmmcUseCustomDlls;
|
||||
|
||||
/** Offset 0x0038 - Emmc Tx CMD Delay control register value
|
||||
Please see Tx CMD Delay Control register definition for help
|
||||
**/
|
||||
UINT32 EmmcTxCmdDelayRegValue;
|
||||
|
||||
/** Offset 0x003C - Emmc Tx DATA Delay control 1 register value
|
||||
Please see Tx DATA Delay control 1 register definition for help
|
||||
**/
|
||||
UINT32 EmmcTxDataDelay1RegValue;
|
||||
|
||||
/** Offset 0x0040 - Emmc Tx DATA Delay control 2 register value
|
||||
Please see Tx DATA Delay control 2 register definition for help
|
||||
**/
|
||||
UINT32 EmmcTxDataDelay2RegValue;
|
||||
|
||||
/** Offset 0x0044 - Emmc Rx CMD + DATA Delay control 1 register value
|
||||
Please see Rx CMD + DATA Delay control 1 register definition for help
|
||||
**/
|
||||
UINT32 EmmcRxCmdDataDelay1RegValue;
|
||||
|
||||
/** Offset 0x0048 - Emmc Rx CMD + DATA Delay control 2 register value
|
||||
Please see Rx CMD + DATA Delay control 2 register definition for help
|
||||
**/
|
||||
UINT32 EmmcRxCmdDataDelay2RegValue;
|
||||
|
||||
/** Offset 0x004C - Emmc Rx Strobe Delay control register value
|
||||
Please see Rx Strobe Delay control register definition for help
|
||||
**/
|
||||
UINT32 EmmcRxStrobeDelayRegValue;
|
||||
|
||||
/** Offset 0x0050 - Enable SdCard Controller
|
||||
Enable/disable SD Card Controller.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 ScsSdCardEnabled;
|
||||
|
||||
/** Offset 0x0051 - SdCard power enable polarity
|
||||
Choose SD_PWREN# polarity
|
||||
0: Active low, 1: Active high
|
||||
**/
|
||||
UINT8 SdCardPowerEnableActiveHigh;
|
||||
|
||||
/** Offset 0x0052 - Reserved
|
||||
**/
|
||||
UINT8 Reserved1[34];
|
||||
|
||||
/** Offset 0x0074 - SdCard Command Pad Termination
|
||||
0x0: Hardware default, 0x1: None, 0x13: 1kOhm weak pull-up, 0x15: 5kOhm weak pull-up,
|
||||
0x19: 20kOhm weak pull-up
|
||||
**/
|
||||
UINT8 SdCardGpioCmdPadTermination;
|
||||
|
||||
/** Offset 0x0075 - Reserved
|
||||
**/
|
||||
UINT8 Reserved2[136];
|
||||
|
||||
/** Offset 0x00FD - Enable SATA SALP Support
|
||||
Enable/disable SATA Aggressive Link Power Management.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 SataSalpSupport;
|
||||
|
||||
/** Offset 0x00FE - Enable SATA ports
|
||||
Enable/disable SATA ports. One byte for each port, byte0 for port0, byte1 for port1,
|
||||
and so on.
|
||||
**/
|
||||
UINT8 SataPortsEnable[8];
|
||||
|
||||
/** Offset 0x0106 - Enable SATA DEVSLP Feature
|
||||
Enable/disable SATA DEVSLP per port. 0 is disable, 1 is enable. One byte for each
|
||||
port, byte0 for port0, byte1 for port1, and so on.
|
||||
**/
|
||||
UINT8 SataPortsDevSlp[8];
|
||||
|
||||
/** Offset 0x010E - Enable USB2 ports
|
||||
Enable/disable per USB2 ports. One byte for each port, byte0 for port0, byte1 for
|
||||
port1, and so on.
|
||||
**/
|
||||
UINT8 PortUsb20Enable[16];
|
||||
|
||||
/** Offset 0x011E - Enable USB3 ports
|
||||
Enable/disable per USB3 ports. One byte for each port, byte0 for port0, byte1 for
|
||||
port1, and so on.
|
||||
**/
|
||||
UINT8 PortUsb30Enable[10];
|
||||
|
||||
/** Offset 0x0128 - Enable xDCI controller
|
||||
Enable/disable to xDCI controller.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 XdciEnable;
|
||||
|
||||
/** Offset 0x0129 - Reserved
|
||||
**/
|
||||
UINT8 Reserved3[28];
|
||||
|
||||
/** Offset 0x0145 - Enable SATA
|
||||
Enable/disable SATA controller.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 SataEnable;
|
||||
|
||||
/** Offset 0x0146 - SATA Mode
|
||||
Select SATA controller working mode.
|
||||
0:AHCI, 1:RAID
|
||||
**/
|
||||
UINT8 SataMode;
|
||||
|
||||
/** Offset 0x0147 - SPIn Device Mode
|
||||
Selects SPI operation mode. N represents controller index: SPI0, SPI1, ... Available
|
||||
modes: 0:SerialIoSpiDisabled, 1:SerialIoSpiPci, 2:SerialIoSpiHidden
|
||||
**/
|
||||
UINT8 SerialIoSpiMode[7];
|
||||
|
||||
/** Offset 0x014E - SPI<N> Chip Select Polarity
|
||||
Sets polarity for each chip Select. Available options: 0:SerialIoSpiCsActiveLow,
|
||||
1:SerialIoSpiCsActiveHigh
|
||||
**/
|
||||
UINT8 SerialIoSpiCsPolarity[14];
|
||||
|
||||
/** Offset 0x015C - Reserved
|
||||
**/
|
||||
UINT8 Reserved4[21];
|
||||
|
||||
/** Offset 0x0171 - SPIn Default Chip Select Mode HW/SW
|
||||
Sets Default CS Mode Hardware or Software. N represents controller index: SPI0,
|
||||
SPI1, ... Available options: 0:HW, 1:SW
|
||||
**/
|
||||
UINT8 SerialIoSpiCsMode[7];
|
||||
|
||||
/** Offset 0x0178 - SPIn Default Chip Select State Low/High
|
||||
Sets Default CS State Low or High. N represents controller index: SPI0, SPI1, ...
|
||||
Available options: 0:Low, 1:High
|
||||
**/
|
||||
UINT8 SerialIoSpiCsState[7];
|
||||
|
||||
/** Offset 0x017F - UARTn Device Mode
|
||||
Selects Uart operation mode. N represents controller index: Uart0, Uart1, ... Available
|
||||
modes: 0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||
4:SerialIoUartSkipInit
|
||||
**/
|
||||
UINT8 SerialIoUartMode[7];
|
||||
|
||||
/** Offset 0x0186 - Reserved
|
||||
**/
|
||||
UINT8 Reserved5[186];
|
||||
|
||||
/** Offset 0x0240 - UART Number For Debug Purpose
|
||||
UART number for debug purpose. 0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5,
|
||||
6:UART6. Note: If UART0 is selected as CNVi BT Core interface, it cannot be used
|
||||
for debug purpose.
|
||||
0:UART0, 1:UART1, 2:UART2, 3:UART3, 4:UART4, 5:UART5, 6:UART6
|
||||
**/
|
||||
UINT8 SerialIoDebugUartNumber;
|
||||
|
||||
/** Offset 0x0241 - Reserved
|
||||
**/
|
||||
UINT8 Reserved6[7];
|
||||
|
||||
/** Offset 0x0248 - I2Cn Device Mode
|
||||
Selects I2c operation mode. N represents controller index: I2c0, I2c1, ... Available
|
||||
modes: 0:SerialIoI2cDisabled, 1:SerialIoI2cPci, 2:SerialIoI2cHidden
|
||||
**/
|
||||
UINT8 SerialIoI2cMode[8];
|
||||
|
||||
/** Offset 0x0250 - Reserved
|
||||
**/
|
||||
UINT8 Reserved7[72];
|
||||
|
||||
/** Offset 0x0298 - USB Per Port HS Preemphasis Bias
|
||||
USB Per Port HS Preemphasis Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
|
||||
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV. One byte for each port.
|
||||
**/
|
||||
UINT8 Usb2PhyPetxiset[16];
|
||||
|
||||
/** Offset 0x02A8 - USB Per Port HS Transmitter Bias
|
||||
USB Per Port HS Transmitter Bias. 000b-0mV, 001b-11.25mV, 010b-16.9mV, 011b-28.15mV,
|
||||
100b-28.15mV, 101b-39.35mV, 110b-45mV, 111b-56.3mV, One byte for each port.
|
||||
**/
|
||||
UINT8 Usb2PhyTxiset[16];
|
||||
|
||||
/** Offset 0x02B8 - USB Per Port HS Transmitter Emphasis
|
||||
USB Per Port HS Transmitter Emphasis. 00b - Emphasis OFF, 01b - De-emphasis ON,
|
||||
10b - Pre-emphasis ON, 11b - Pre-emphasis & De-emphasis ON. One byte for each port.
|
||||
**/
|
||||
UINT8 Usb2PhyPredeemp[16];
|
||||
|
||||
/** Offset 0x02C8 - USB Per Port Half Bit Pre-emphasis
|
||||
USB Per Port Half Bit Pre-emphasis. 1b - half-bit pre-emphasis, 0b - full-bit pre-emphasis.
|
||||
One byte for each port.
|
||||
**/
|
||||
UINT8 Usb2PhyPehalfbit[16];
|
||||
|
||||
/** Offset 0x02D8 - Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment
|
||||
Enable the write to USB 3.0 TX Output -3.5dB De-Emphasis Adjustment. Each value
|
||||
in arrary can be between 0-1. One byte for each port.
|
||||
**/
|
||||
UINT8 Usb3HsioTxDeEmphEnable[10];
|
||||
|
||||
/** Offset 0x02E2 - USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting
|
||||
USB 3.0 TX Output -3.5dB De-Emphasis Adjustment Setting, HSIO_TX_DWORD5[21:16],
|
||||
<b>Default = 29h</b> (approximately -3.5dB De-Emphasis). One byte for each port.
|
||||
**/
|
||||
UINT8 Usb3HsioTxDeEmph[10];
|
||||
|
||||
/** Offset 0x02EC - Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment
|
||||
Enable the write to USB 3.0 TX Output Downscale Amplitude Adjustment, Each value
|
||||
in arrary can be between 0-1. One byte for each port.
|
||||
**/
|
||||
UINT8 Usb3HsioTxDownscaleAmpEnable[10];
|
||||
|
||||
/** Offset 0x02F6 - USB 3.0 TX Output Downscale Amplitude Adjustment
|
||||
USB 3.0 TX Output Downscale Amplitude Adjustment, HSIO_TX_DWORD8[21:16], <b>Default
|
||||
= 00h</b>. One byte for each port.
|
||||
**/
|
||||
UINT8 Usb3HsioTxDownscaleAmp[10];
|
||||
|
||||
/** Offset 0x0300 - Enable LAN
|
||||
Enable/disable LAN controller.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PchLanEnable;
|
||||
|
||||
/** Offset 0x0301 - Reserved
|
||||
**/
|
||||
UINT8 Reserved8[83];
|
||||
|
||||
/** Offset 0x0354 - External V1P05 Voltage Value that will be used in S0i2/S0i3 states
|
||||
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
|
||||
**/
|
||||
UINT16 PchFivrExtV1p05RailVoltage;
|
||||
|
||||
/** Offset 0x0356 - External V1P05 Icc Max Value
|
||||
Granularity of this setting is 1mA and maximal possible value is 200mA
|
||||
**/
|
||||
UINT8 PchFivrExtV1p05RailIccMax;
|
||||
|
||||
/** Offset 0x0357 - Reserved
|
||||
**/
|
||||
UINT8 Reserved9;
|
||||
|
||||
/** Offset 0x0358 - External Vnn Voltage Value that will be used in S0ix/Sx states
|
||||
Value is given in 2.5mV increments (0=0mV, 1=2.5mV, 2=5mV...)
|
||||
**/
|
||||
UINT16 PchFivrExtVnnRailVoltage;
|
||||
|
||||
/** Offset 0x035A - External Vnn Icc Max Value that will be used in S0ix/Sx states
|
||||
Granularity of this setting is 1mA and maximal possible value is 200mA
|
||||
**/
|
||||
UINT8 PchFivrExtVnnRailIccMax;
|
||||
|
||||
/** Offset 0x035B - Reserved
|
||||
**/
|
||||
UINT8 Reserved10;
|
||||
|
||||
/** Offset 0x035C - External Vnn Voltage Value that will be used in Sx states
|
||||
Use only if Ext Vnn Rail config is different in Sx. Value is given in 2.5mV increments
|
||||
(0=0mV, 1=2.5mV, 2=5mV...)
|
||||
**/
|
||||
UINT16 PchFivrExtVnnRailSxVoltage;
|
||||
|
||||
/** Offset 0x035E - External Vnn Icc Max Value that will be used in Sx states
|
||||
Use only if Ext Vnn Rail config is different in Sx. Granularity of this setting
|
||||
is 1mA and maximal possible value is 200mA
|
||||
**/
|
||||
UINT8 PchFivrExtVnnRailSxIccMax;
|
||||
|
||||
/** Offset 0x035F - Reserved
|
||||
**/
|
||||
UINT8 Reserved11[3];
|
||||
|
||||
/** Offset 0x0362 - Transition time in microseconds from Off (0V) to High Current Mode Voltage
|
||||
This field has 1us resolution. When value is 0 Transition to 0V is disabled.
|
||||
**/
|
||||
UINT16 PchFivrVccinAuxOffToHighCurModeVolTranTime;
|
||||
|
||||
/** Offset 0x0364 - Reserved
|
||||
**/
|
||||
UINT8 Reserved12[22];
|
||||
|
||||
/** Offset 0x037A - CNVi BT Audio Offload
|
||||
Enable/Disable BT Audio Offload, Default is DISABLE. 0: DISABLE, 1: ENABLE
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 CnviBtAudioOffload;
|
||||
|
||||
/** Offset 0x037B - Reserved
|
||||
**/
|
||||
UINT8 Reserved13;
|
||||
|
||||
/** Offset 0x037C - CNVi RF_RESET pin muxing
|
||||
Select CNVi RF_RESET# pin depending on board routing. ICP-N: GPP_H12 = 0x2746E40C(default)
|
||||
or GPP_H1 = 0x3746E401. Refer to GPIO_*_MUXING_CNVI_RF_RESET_* in GpioPins*.h.
|
||||
**/
|
||||
UINT32 CnviRfResetPinMux;
|
||||
|
||||
/** Offset 0x0380 - CNVi CLKREQ pin muxing
|
||||
Select CNVi CLKREQ pin depending on board routing. ICP-N: GPP_H13 = 0x2746E60D(default)
|
||||
or GPP_H2 = 0x3746E602. Refer to GPIO_*_MUXING_CNVI_MODEM_CLKREQ_* in GpioPins*.h.
|
||||
**/
|
||||
UINT32 CnviClkreqPinMux;
|
||||
|
||||
/** Offset 0x0384 - Reserved
|
||||
**/
|
||||
UINT8 Reserved14[6];
|
||||
|
||||
/** Offset 0x038A - HECI3 state
|
||||
The HECI3 state from Mbp for reference in S3 path or when MbpHob is not installed.
|
||||
0: disable, 1: enable
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 Heci3Enabled;
|
||||
|
||||
/** Offset 0x038B - Reserved
|
||||
**/
|
||||
UINT8 Reserved15[141];
|
||||
|
||||
/** Offset 0x0418 - CdClock Frequency selection
|
||||
0: (Default) Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180
|
||||
Mhz, 3: 190 Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz,
|
||||
9: 652.8 Mhz
|
||||
0: Auto (Max based on reference clock frequency), 1: 172.8 Mhz, 2: 180 Mhz, 3: 190
|
||||
Mhz, 4: 307.2 Mhz, 5: 312 Mhz, 6: 552 Mhz, 7: 556.8 Mhz, 8: 648 Mhz, 9: 652.8 Mhz
|
||||
**/
|
||||
UINT8 CdClock;
|
||||
|
||||
/** Offset 0x0419 - Enable/Disable PeiGraphicsPeimInit
|
||||
Enable: Enable PeiGraphicsPeimInit, Disable(Default): Disable PeiGraphicsPeimInit
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PeiGraphicsPeimInit;
|
||||
|
||||
/** Offset 0x041A - Reserved
|
||||
**/
|
||||
UINT8 Reserved16[160];
|
||||
|
||||
/** Offset 0x04BA - Skip Multi-Processor Initialization
|
||||
When this is skipped, boot loader must initialize processors before SilicionInit
|
||||
API. </b>0: Initialize; <b>1: Skip
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 SkipMpInit;
|
||||
|
||||
/** Offset 0x04BB - Reserved
|
||||
**/
|
||||
UINT8 Reserved17[9];
|
||||
|
||||
/** Offset 0x04C4 - CpuMpPpi
|
||||
Pointer for CpuMpPpi
|
||||
**/
|
||||
UINT32 CpuMpPpi;
|
||||
|
||||
/** Offset 0x04C8 - Reserved
|
||||
**/
|
||||
UINT8 Reserved18[86];
|
||||
|
||||
/** Offset 0x051E - RTC Cmos Memory Lock
|
||||
Enable RTC lower and upper 128 byte Lock bits to lock Bytes 38h-3Fh in the upper
|
||||
and and lower 128-byte bank of RTC RAM.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 RtcMemoryLock;
|
||||
|
||||
/** Offset 0x051F - Reserved
|
||||
**/
|
||||
UINT8 Reserved19[24];
|
||||
|
||||
/** Offset 0x0537 - Enable PCIE RP Pm Sci
|
||||
Indicate whether the root port power manager SCI is enabled.
|
||||
**/
|
||||
UINT8 PcieRpPmSci[24];
|
||||
|
||||
/** Offset 0x054F - Reserved
|
||||
**/
|
||||
UINT8 Reserved20[24];
|
||||
|
||||
/** Offset 0x0567 - Enable PCIE RP Clk Req Detect
|
||||
Probe CLKREQ# signal before enabling CLKREQ# based power management.
|
||||
**/
|
||||
UINT8 PcieRpClkReqDetect[24];
|
||||
|
||||
/** Offset 0x057F - Reserved
|
||||
**/
|
||||
UINT8 Reserved21[455];
|
||||
|
||||
/** Offset 0x0746 - PCH Pm Slp S3 Min Assert
|
||||
SLP_S3 Minimum Assertion Width Policy. Default is PchSlpS350ms.
|
||||
**/
|
||||
UINT8 PchPmSlpS3MinAssert;
|
||||
|
||||
/** Offset 0x0747 - Reserved
|
||||
**/
|
||||
UINT8 Reserved22;
|
||||
|
||||
/** Offset 0x0748 - PCH Pm Slp Sus Min Assert
|
||||
SLP_SUS Minimum Assertion Width Policy. Default is PchSlpSus4s.
|
||||
**/
|
||||
UINT8 PchPmSlpSusMinAssert;
|
||||
|
||||
/** Offset 0x0749 - PCH Pm Slp A Min Assert
|
||||
SLP_A Minimum Assertion Width Policy. Default is PchSlpA2s.
|
||||
**/
|
||||
UINT8 PchPmSlpAMinAssert;
|
||||
|
||||
/** Offset 0x074A - Reserved
|
||||
**/
|
||||
UINT8 Reserved23[11];
|
||||
|
||||
/** Offset 0x0755 - PCH Sata Pwr Opt Enable
|
||||
SATA Power Optimizer on PCH side.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 SataPwrOptEnable;
|
||||
|
||||
/** Offset 0x0756 - Reserved
|
||||
**/
|
||||
UINT8 Reserved24[146];
|
||||
|
||||
/** Offset 0x07E8 - USB2 Port Over Current Pin
|
||||
Describe the specific over current pin number of USB 2.0 Port N.
|
||||
**/
|
||||
UINT8 Usb2OverCurrentPin[16];
|
||||
|
||||
/** Offset 0x07F8 - USB3 Port Over Current Pin
|
||||
Describe the specific over current pin number of USB 3.0 Port N.
|
||||
**/
|
||||
UINT8 Usb3OverCurrentPin[10];
|
||||
|
||||
/** Offset 0x0802 - Enable 8254 Static Clock Gating
|
||||
Set 8254CGE=1 is required for SLP_S0 support. However, set 8254CGE=1 in POST time
|
||||
might fail to boot legacy OS using 8254 timer. Make sure it is disabled to support
|
||||
legacy OS using 8254 timer. Also enable this while S0ix is enabled.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 Enable8254ClockGating;
|
||||
|
||||
/** Offset 0x0803 - Enable 8254 Static Clock Gating On S3
|
||||
This is only applicable when Enable8254ClockGating is disabled. FSP will do the
|
||||
8254 CGE programming on S3 resume when Enable8254ClockGatingOnS3 is enabled. This
|
||||
avoids the SMI requirement for the programming.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 Enable8254ClockGatingOnS3;
|
||||
|
||||
/** Offset 0x0804 - Reserved
|
||||
**/
|
||||
UINT8 Reserved25[531];
|
||||
|
||||
/** Offset 0x0A17 - Enable/Disable IGFX PmSupport
|
||||
Enable(Default): Enable IGFX PmSupport, Disable: Disable IGFX PmSupport
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PmSupport;
|
||||
|
||||
/** Offset 0x0A18 - Reserved
|
||||
**/
|
||||
UINT8 Reserved26[32];
|
||||
|
||||
/** Offset 0x0A38 - TCC Activation Offset
|
||||
TCC Activation Offset. Offset from factory set TCC activation temperature at which
|
||||
the Thermal Control Circuit must be activated. TCC will be activated at TCC Activation
|
||||
Temperature, in volts.For SKL Y SKU, the recommended default for this policy is
|
||||
<b>10</b>, For all other SKUs the recommended default are <b>0</b>
|
||||
**/
|
||||
UINT8 TccActivationOffset;
|
||||
|
||||
/** Offset 0x0A39 - Reserved
|
||||
**/
|
||||
UINT8 Reserved27[34];
|
||||
|
||||
/** Offset 0x0A5B - Enable or Disable CPU power states (C-states)
|
||||
Enable or Disable CPU power states (C-states). 0: Disable; <b>1: Enable</b>
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 Cx;
|
||||
|
||||
/** Offset 0x0A5C - Reserved
|
||||
**/
|
||||
UINT8 Reserved28[74];
|
||||
|
||||
/** Offset 0x0AA6 - Platform Power Pmax
|
||||
PCODE MMIO Mailbox: Platform Power Pmax. <b>0 - Auto</b> Specified in 1/8 Watt increments.
|
||||
Range 0-1024 Watts. Value of 800 = 100W
|
||||
**/
|
||||
UINT16 PsysPmax;
|
||||
|
||||
/** Offset 0x0AA8 - Reserved
|
||||
**/
|
||||
UINT8 Reserved29[116];
|
||||
|
||||
/** Offset 0x0B1C - End of Post message
|
||||
Test, Send End of Post message. Disable(0x0): Disable EOP message, Send in PEI(0x1):
|
||||
EOP send in PEI, Send in DXE(0x2)(Default): EOP send in DXE
|
||||
0:Disable, 1:Send in PEI, 2:Send in DXE, 3:Reserved
|
||||
**/
|
||||
UINT8 EndOfPostMessage;
|
||||
|
||||
/** Offset 0x0B1D - Reserved
|
||||
**/
|
||||
UINT8 Reserved30[3];
|
||||
|
||||
/** Offset 0x0B20 - Unlock all GPIO pads
|
||||
Force all GPIO pads to be unlocked for debug purpose.
|
||||
$EN_DIS
|
||||
**/
|
||||
UINT8 PchUnlockGpioPads;
|
||||
|
||||
/** Offset 0x0B21 - Reserved
|
||||
**/
|
||||
UINT8 Reserved31[447];
|
||||
} FSP_S_CONFIG;
|
||||
|
||||
/** Fsp S UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSP_S_CONFIG FspsConfig;
|
||||
|
||||
/** Offset 0x0CE0
|
||||
**/
|
||||
UINT8 UnusedUpdSpace37[6];
|
||||
|
||||
/** Offset 0x0CE6
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPS_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,186 @@
|
|||
/** @file
|
||||
|
||||
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
||||
|
||||
Redistribution and use in source and binary forms, with or without modification,
|
||||
are permitted provided that the following conditions are met:
|
||||
|
||||
* Redistributions of source code must retain the above copyright notice, this
|
||||
list of conditions and the following disclaimer.
|
||||
* Redistributions in binary form must reproduce the above copyright notice, this
|
||||
list of conditions and the following disclaimer in the documentation and/or
|
||||
other materials provided with the distribution.
|
||||
* Neither the name of Intel Corporation nor the names of its contributors may
|
||||
be used to endorse or promote products derived from this software without
|
||||
specific prior written permission.
|
||||
|
||||
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
|
||||
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
|
||||
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
|
||||
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
|
||||
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
|
||||
CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
|
||||
SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
|
||||
INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
|
||||
CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
|
||||
ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
|
||||
THE POSSIBILITY OF SUCH DAMAGE.
|
||||
|
||||
This file is automatically generated. Please do NOT modify !!!
|
||||
|
||||
**/
|
||||
|
||||
#ifndef __FSPTUPD_H__
|
||||
#define __FSPTUPD_H__
|
||||
|
||||
#include <FspUpd.h>
|
||||
|
||||
#pragma pack(1)
|
||||
|
||||
|
||||
/** Fsp T Core UPD
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
UINT32 MicrocodeRegionBase;
|
||||
|
||||
/** Offset 0x0024
|
||||
**/
|
||||
UINT32 MicrocodeRegionSize;
|
||||
|
||||
/** Offset 0x0028
|
||||
**/
|
||||
UINT32 CodeRegionBase;
|
||||
|
||||
/** Offset 0x002C
|
||||
**/
|
||||
UINT32 CodeRegionSize;
|
||||
|
||||
/** Offset 0x0030
|
||||
**/
|
||||
UINT8 Reserved[16];
|
||||
} FSPT_CORE_UPD;
|
||||
|
||||
/** Fsp T Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0040 - PcdSerialIoUartDebugEnable
|
||||
Enable SerialIo Uart debug library with/without initializing SerialIo Uart device in FSP.
|
||||
0:Disable, 1:Enable and Initialize, 2:Enable without Initializing
|
||||
**/
|
||||
UINT8 PcdSerialIoUartDebugEnable;
|
||||
|
||||
/** Offset 0x0041 - PcdSerialIoUartNumber - FSPT
|
||||
Select SerialIo Uart Controller for debug. Note: If UART0 is selected as CNVi BT
|
||||
Core interface, it cannot be used for debug purpose.
|
||||
0:SerialIoUart0, 1:SerialIoUart1, 2:SerialIoUart2
|
||||
**/
|
||||
UINT8 PcdSerialIoUartNumber;
|
||||
|
||||
/** Offset 0x0042 - PcdSerialIoUartMode - FSPT
|
||||
Select SerialIo Uart Controller mode
|
||||
0:SerialIoUartDisabled, 1:SerialIoUartPci, 2:SerialIoUartHidden, 3:SerialIoUartCom,
|
||||
4:SerialIoUartSkipInit
|
||||
**/
|
||||
UINT8 PcdSerialIoUartMode;
|
||||
|
||||
/** Offset 0x0043
|
||||
**/
|
||||
UINT8 UnusedUpdSpace0;
|
||||
|
||||
/** Offset 0x0044 - PcdSerialIoUartBaudRate - FSPT
|
||||
Set default BaudRate Supported from 0 - default to 6000000
|
||||
**/
|
||||
UINT32 PcdSerialIoUartBaudRate;
|
||||
|
||||
/** Offset 0x0048 - Pci Express Base Address
|
||||
Base address to be programmed for Pci Express
|
||||
**/
|
||||
UINT64 PcdPciExpressBaseAddress;
|
||||
|
||||
/** Offset 0x0050 - Pci Express Region Length
|
||||
Region Length to be programmed for Pci Express
|
||||
**/
|
||||
UINT32 PcdPciExpressRegionLength;
|
||||
|
||||
/** Offset 0x0054 - PcdSerialIoUartParity - FSPT
|
||||
Set default Parity.
|
||||
0: DefaultParity, 1: NoParity, 2: EvenParity, 3: OddParity
|
||||
**/
|
||||
UINT8 PcdSerialIoUartParity;
|
||||
|
||||
/** Offset 0x0055 - PcdSerialIoUartDataBits - FSPT
|
||||
Set default word length. 0: Default, 5,6,7,8
|
||||
**/
|
||||
UINT8 PcdSerialIoUartDataBits;
|
||||
|
||||
/** Offset 0x0056 - PcdSerialIoUartStopBits - FSPT
|
||||
Set default stop bits.
|
||||
0: DefaultStopBits, 1: OneStopBit, 2: OneFiveStopBits, 3: TwoStopBits
|
||||
**/
|
||||
UINT8 PcdSerialIoUartStopBits;
|
||||
|
||||
/** Offset 0x0057 - PcdSerialIoUartAutoFlow - FSPT
|
||||
Enables UART hardware flow control, CTS and RTS lines.
|
||||
0: Disable, 1:Enable
|
||||
**/
|
||||
UINT8 PcdSerialIoUartAutoFlow;
|
||||
|
||||
/** Offset 0x0058 - PcdSerialIoUartRxPinMux - FSPT
|
||||
Select RX pin muxing for SerialIo UART used for debug
|
||||
**/
|
||||
UINT32 PcdSerialIoUartRxPinMux;
|
||||
|
||||
/** Offset 0x005C - PcdSerialIoUartTxPinMux - FSPT
|
||||
Select TX pin muxing for SerialIo UART used for debug
|
||||
**/
|
||||
UINT32 PcdSerialIoUartTxPinMux;
|
||||
|
||||
/** Offset 0x0060 - PcdSerialIoUartRtsPinMux - FSPT
|
||||
Select SerialIo Uart used for debug Rts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_RTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartRtsPinMux;
|
||||
|
||||
/** Offset 0x0064 - PcdSerialIoUartCtsPinMux - FSPT
|
||||
Select SerialIo Uart used for debug Cts pin muxing. Refer to GPIO_*_MUXING_SERIALIO_UARTx_CTS*
|
||||
for possible values.
|
||||
**/
|
||||
UINT32 PcdSerialIoUartCtsPinMux;
|
||||
|
||||
/** Offset 0x0068
|
||||
**/
|
||||
UINT8 ReservedFsptUpd1[24];
|
||||
} FSP_T_CONFIG;
|
||||
|
||||
/** Fsp T UPD Configuration
|
||||
**/
|
||||
typedef struct {
|
||||
|
||||
/** Offset 0x0000
|
||||
**/
|
||||
FSP_UPD_HEADER FspUpdHeader;
|
||||
|
||||
/** Offset 0x0020
|
||||
**/
|
||||
FSPT_CORE_UPD FsptCoreUpd;
|
||||
|
||||
/** Offset 0x0040
|
||||
**/
|
||||
FSP_T_CONFIG FsptConfig;
|
||||
|
||||
/** Offset 0x0080
|
||||
**/
|
||||
UINT8 UnusedUpdSpace1[6];
|
||||
|
||||
/** Offset 0x0086
|
||||
**/
|
||||
UINT16 UpdTerminator;
|
||||
} FSPT_UPD;
|
||||
|
||||
#pragma pack()
|
||||
|
||||
#endif
|
||||
|
|
@ -0,0 +1,274 @@
|
|||
/** @file
|
||||
This file contains definitions required for creation of
|
||||
Memory S3 Save data, Memory Info data and Memory Platform
|
||||
data hobs.
|
||||
|
||||
@copyright
|
||||
Copyright (c) 2019, Intel Corporation. All rights reserved.<BR>
|
||||
This program and the accompanying materials are licensed and made available under
|
||||
the terms and conditions of the BSD License that accompanies this distribution.
|
||||
The full text of the license may be found at
|
||||
http://opensource.org/licenses/bsd-license.php.
|
||||
THE PROGRAM IS DISTRIBUTED UNDER THE BSD LICENSE ON AN "AS IS" BASIS,
|
||||
|
||||
WITHOUT WARRANTIES OR REPRESENTATIONS OF ANY KIND, EITHER EXPRESS OR IMPLIED.
|
||||
|
||||
@par Specification Reference:
|
||||
**/
|
||||
#ifndef _MEM_INFO_HOB_H_
|
||||
#define _MEM_INFO_HOB_H_
|
||||
|
||||
#include <Uefi/UefiMultiPhase.h>
|
||||
#include <Pi/PiBootMode.h>
|
||||
#include <Pi/PiHob.h>
|
||||
|
||||
#pragma pack (push, 1)
|
||||
|
||||
extern EFI_GUID gSiMemoryS3DataGuid;
|
||||
extern EFI_GUID gSiMemoryInfoDataGuid;
|
||||
extern EFI_GUID gSiMemoryPlatformDataGuid;
|
||||
|
||||
#define MAX_NODE 1
|
||||
#define MAX_CH 2
|
||||
#define MAX_DIMM 2
|
||||
|
||||
///
|
||||
/// Host reset states from MRC.
|
||||
///
|
||||
#define WARM_BOOT 2
|
||||
|
||||
#define R_MC_CHNL_RANK_PRESENT 0x7C
|
||||
#define B_RANK0_PRS BIT0
|
||||
#define B_RANK1_PRS BIT1
|
||||
#define B_RANK2_PRS BIT4
|
||||
#define B_RANK3_PRS BIT5
|
||||
|
||||
///
|
||||
/// Defines taken from MRC so avoid having to include MrcInterface.h
|
||||
///
|
||||
|
||||
//
|
||||
// Matches MAX_SPD_SAVE define in MRC
|
||||
//
|
||||
#ifndef MAX_SPD_SAVE
|
||||
#define MAX_SPD_SAVE 29
|
||||
#endif
|
||||
|
||||
//
|
||||
// MRC version description.
|
||||
//
|
||||
typedef struct {
|
||||
UINT8 Major; ///< Major version number
|
||||
UINT8 Minor; ///< Minor version number
|
||||
UINT8 Rev; ///< Revision number
|
||||
UINT8 Build; ///< Build number
|
||||
} SiMrcVersion;
|
||||
|
||||
//
|
||||
// Matches MrcChannelSts enum in MRC
|
||||
//
|
||||
#ifndef CHANNEL_NOT_PRESENT
|
||||
#define CHANNEL_NOT_PRESENT 0 // There is no channel present on the controller.
|
||||
#endif
|
||||
#ifndef CHANNEL_DISABLED
|
||||
#define CHANNEL_DISABLED 1 // There is a channel present but it is disabled.
|
||||
#endif
|
||||
#ifndef CHANNEL_PRESENT
|
||||
#define CHANNEL_PRESENT 2 // There is a channel present and it is enabled.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDimmSts enum in MRC
|
||||
//
|
||||
#ifndef DIMM_ENABLED
|
||||
#define DIMM_ENABLED 0 // DIMM/rank Pair is enabled, presence will be detected.
|
||||
#endif
|
||||
#ifndef DIMM_DISABLED
|
||||
#define DIMM_DISABLED 1 // DIMM/rank Pair is disabled, regardless of presence.
|
||||
#endif
|
||||
#ifndef DIMM_PRESENT
|
||||
#define DIMM_PRESENT 2 // There is a DIMM present in the slot/rank pair and it will be used.
|
||||
#endif
|
||||
#ifndef DIMM_NOT_PRESENT
|
||||
#define DIMM_NOT_PRESENT 3 // There is no DIMM present in the slot/rank pair.
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcBootMode enum in MRC
|
||||
//
|
||||
#ifndef bmCold
|
||||
#define bmCold 0 // Cold boot
|
||||
#endif
|
||||
#ifndef bmWarm
|
||||
#define bmWarm 1 // Warm boot
|
||||
#endif
|
||||
#ifndef bmS3
|
||||
#define bmS3 2 // S3 resume
|
||||
#endif
|
||||
#ifndef bmFast
|
||||
#define bmFast 3 // Fast boot
|
||||
#endif
|
||||
|
||||
//
|
||||
// Matches MrcDdrType enum in MRC
|
||||
//
|
||||
#ifndef MRC_DDR_TYPE_DDR4
|
||||
#define MRC_DDR_TYPE_DDR4 0
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_DDR3
|
||||
#define MRC_DDR_TYPE_DDR3 1
|
||||
#endif
|
||||
#ifndef MRC_DDR_TYPE_LPDDR3
|
||||
#define MRC_DDR_TYPE_LPDDR3 2
|
||||
#endif
|
||||
#ifndef CPU_CFL//CNL
|
||||
#ifndef MRC_DDR_TYPE_LPDDR4
|
||||
#define MRC_DDR_TYPE_LPDDR4 3
|
||||
#endif
|
||||
#else//CFL
|
||||
#ifndef MRC_DDR_TYPE_UNKNOWN
|
||||
#define MRC_DDR_TYPE_UNKNOWN 3
|
||||
#endif
|
||||
#endif//CPU_CFL-endif
|
||||
|
||||
#define MAX_PROFILE_NUM 4 // number of memory profiles supported
|
||||
#define MAX_XMP_PROFILE_NUM 2 // number of XMP profiles supported
|
||||
|
||||
//
|
||||
// DIMM timings
|
||||
//
|
||||
typedef struct {
|
||||
UINT32 tCK; ///< Memory cycle time, in femtoseconds.
|
||||
UINT16 NMode; ///< Number of tCK cycles for the channel DIMM's command rate mode.
|
||||
UINT16 tCL; ///< Number of tCK cycles for the channel DIMM's CAS latency.
|
||||
UINT16 tCWL; ///< Number of tCK cycles for the channel DIMM's minimum CAS write latency time.
|
||||
UINT16 tFAW; ///< Number of tCK cycles for the channel DIMM's minimum four activate window delay time.
|
||||
UINT16 tRAS; ///< Number of tCK cycles for the channel DIMM's minimum active to precharge delay time.
|
||||
UINT16 tRCDtRP; ///< Number of tCK cycles for the channel DIMM's minimum RAS# to CAS# delay time and Row Precharge delay time.
|
||||
UINT16 tREFI; ///< Number of tCK cycles for the channel DIMM's minimum Average Periodic Refresh Interval.
|
||||
UINT16 tRFC; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFCpb; ///< Number of tCK cycles for the channel DIMM's minimum per bank refresh recovery delay time.
|
||||
UINT16 tRFC2; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRFC4; ///< Number of tCK cycles for the channel DIMM's minimum refresh recovery delay time.
|
||||
UINT16 tRPab; ///< Number of tCK cycles for the channel DIMM's minimum row precharge delay time for all banks.
|
||||
UINT16 tRRD; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time.
|
||||
UINT16 tRRD_L; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for same bank groups.
|
||||
UINT16 tRRD_S; ///< Number of tCK cycles for the channel DIMM's minimum row active to row active delay time for different bank groups.
|
||||
UINT16 tRTP; ///< Number of tCK cycles for the channel DIMM's minimum internal read to precharge command delay time.
|
||||
UINT16 tWR; ///< Number of tCK cycles for the channel DIMM's minimum write recovery time.
|
||||
UINT16 tWTR; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time.
|
||||
UINT16 tWTR_L; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for same bank groups.
|
||||
UINT16 tWTR_S; ///< Number of tCK cycles for the channel DIMM's minimum internal write to read command delay time for different bank groups.
|
||||
UINT16 tCCD_L; ///< Number of tCK cycles for the channel DIMM's minimum CAS-to-CAS delay for same bank group.
|
||||
} MRC_CH_TIMING;
|
||||
|
||||
typedef struct {
|
||||
UINT8 SG; ///< Number of tCK cycles between transactions in the same bank group.
|
||||
UINT8 DG; ///< Number of tCK cycles between transactions when switching bank groups.
|
||||
UINT8 DR; ///< Number of tCK cycles between transactions when switching between Ranks (in the same DIMM).
|
||||
UINT8 DD; ///< Number of tCK cycles between transactions when switching between DIMMs.
|
||||
} MRC_TA_TIMING;
|
||||
|
||||
///
|
||||
/// Memory SMBIOS & OC Memory Data Hob
|
||||
///
|
||||
typedef struct {
|
||||
UINT8 Status; ///< See MrcDimmStatus for the definition of this field.
|
||||
UINT8 DimmId;
|
||||
UINT32 DimmCapacity; ///< DIMM size in MBytes.
|
||||
UINT16 MfgId;
|
||||
UINT8 ModulePartNum[20]; ///< Module part number for DDR3 is 18 bytes however for DRR4 20 bytes as per JEDEC Spec, so reserving 20 bytes
|
||||
UINT8 RankInDimm; ///< The number of ranks in this DIMM.
|
||||
UINT8 SpdDramDeviceType; ///< Save SPD DramDeviceType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleType; ///< Save SPD ModuleType information needed for SMBIOS structure creation.
|
||||
UINT8 SpdModuleMemoryBusWidth; ///< Save SPD ModuleMemoryBusWidth information needed for SMBIOS structure creation.
|
||||
UINT8 SpdSave[MAX_SPD_SAVE]; ///< Save SPD Manufacturing information needed for SMBIOS structure creation.
|
||||
UINT16 Speed; ///< The maximum capable speed of the device, in MHz.
|
||||
} DIMM_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this channel should be used.
|
||||
UINT8 ChannelId;
|
||||
UINT8 DimmCount; ///< Number of valid DIMMs that exist in the channel.
|
||||
MRC_CH_TIMING Timing[MAX_PROFILE_NUM]; ///< The channel timing values.
|
||||
DIMM_INFO DimmInfo[MAX_DIMM]; ///< Save the DIMM output characteristics.
|
||||
MRC_TA_TIMING tRd2Rd; ///< Read-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tRd2Wr; ///< Read-to-Write Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Rd; ///< Write-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Wr; ///< Write-to-Write Turn Around Timings
|
||||
} CHANNEL_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Status; ///< Indicates whether this controller should be used.
|
||||
UINT16 DeviceId; ///< The PCI device id of this memory controller.
|
||||
UINT8 RevisionId; ///< The PCI revision id of this memory controller.
|
||||
UINT8 ChannelCount; ///< Number of valid channels that exist on the controller.
|
||||
CHANNEL_INFO ChannelInfo[MAX_CH]; ///< The following are channel level definitions.
|
||||
MRC_TA_TIMING tRd2Rd; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tRd2Wr; ///< Deprecated and moved to CHANNEL_INFO. Read-to-Write Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Rd; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Read Turn Around Timings
|
||||
MRC_TA_TIMING tWr2Wr; ///< Deprecated and moved to CHANNEL_INFO. Write-to-Write Turn Around Timings
|
||||
} CONTROLLER_INFO;
|
||||
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT16 DataWidth; ///< Data width, in bits, of this memory device
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.18.2 and Table 75
|
||||
**/
|
||||
UINT8 MemoryType; ///< DDR type: DDR3, DDR4, or LPDDR3
|
||||
UINT16 MaximumMemoryClockSpeed;///< The maximum capable speed of the device, in megahertz (MHz)
|
||||
UINT16 ConfiguredMemoryClockSpeed; ///< The configured clock speed to the memory device, in megahertz (MHz)
|
||||
/** As defined in SMBIOS 3.0 spec
|
||||
Section 7.17.3 and Table 72
|
||||
**/
|
||||
UINT8 ErrorCorrectionType;
|
||||
|
||||
SiMrcVersion Version;
|
||||
BOOLEAN EccSupport;
|
||||
UINT8 MemoryProfile;
|
||||
UINT32 TotalPhysicalMemorySize;
|
||||
UINT32 DefaultXmptCK[MAX_XMP_PROFILE_NUM];///< Stores the tCK value read from SPD XMP profiles if they exist.
|
||||
UINT8 XmpProfileEnable; ///< If XMP capable DIMMs are detected, this will indicate which XMP Profiles are common among all DIMMs.
|
||||
UINT8 Ratio;
|
||||
UINT8 RefClk;
|
||||
UINT32 VddVoltage[MAX_PROFILE_NUM];
|
||||
CONTROLLER_INFO Controller[MAX_NODE];
|
||||
} MEMORY_INFO_DATA_HOB;
|
||||
|
||||
/**
|
||||
Memory Platform Data Hob
|
||||
|
||||
<b>Revision 1:</b>
|
||||
- Initial version.
|
||||
<b>Revision 2:</b>
|
||||
- Added TsegBase, PrmrrSize, PrmrrBase, Gttbase, MmioSize, PciEBaseAddress fields
|
||||
**/
|
||||
typedef struct {
|
||||
UINT8 Revision;
|
||||
UINT8 Reserved[3];
|
||||
UINT32 BootMode;
|
||||
UINT32 TsegSize;
|
||||
UINT32 TsegBase;
|
||||
UINT32 PrmrrSize;
|
||||
UINT32 PrmrrBase;
|
||||
UINT32 GttBase;
|
||||
UINT32 MmioSize;
|
||||
UINT32 PciEBaseAddress;
|
||||
#ifdef CPU_CFL
|
||||
UINT32 GdxcIotBase;
|
||||
UINT32 GdxcIotSize;
|
||||
UINT32 GdxcMotBase;
|
||||
UINT32 GdxcMotSize;
|
||||
#endif //CPU_CFL
|
||||
} MEMORY_PLATFORM_DATA;
|
||||
|
||||
typedef struct {
|
||||
EFI_HOB_GUID_TYPE EfiHobGuidType;
|
||||
MEMORY_PLATFORM_DATA Data;
|
||||
UINT8 *Buffer;
|
||||
} MEMORY_PLATFORM_DATA_HOB;
|
||||
|
||||
#pragma pack (pop)
|
||||
|
||||
#endif // _MEM_INFO_HOB_H_
|
||||
Loading…
Reference in New Issue