mb/cubietech/cubieboard: Remove board
The Allwinner code was never completed and lacks a driver to load romstage from the bootblock. Change-Id: I12e9d7213ce61ab757e9317a63299d5d82e69acb Signed-off-by: Arthur Heymans <arthur@aheymans.xyz> Reviewed-on: https://review.coreboot.org/c/coreboot/+/33132 Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans
Patrick Georgi
parent
2e92adce77
commit
041200fae3
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@ -1,17 +0,0 @@
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if VENDOR_CUBIETECH
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# Auto select common options
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choice
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prompt "Mainboard model"
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source "src/mainboard/cubietech/*/Kconfig.name"
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endchoice
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source "src/mainboard/cubietech/*/Kconfig"
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config MAINBOARD_VENDOR
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string
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default "Cubietech"
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endif # VENDOR_CUBIETECH
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@ -1,2 +0,0 @@
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config VENDOR_CUBIETECH
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bool "Cubietech"
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@ -1,30 +0,0 @@
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if BOARD_CUBIETECH_CUBIEBOARD
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config BOARD_SPECIFIC_OPTIONS
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def_bool y
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select CPU_ALLWINNER_A10
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select BOARD_ROMSIZE_KB_4096
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select DRIVER_XPOWERS_AXP209
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select MISSING_BOARD_RESET
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config MAINBOARD_DIR
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string
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default cubietech/cubieboard
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config MAINBOARD_PART_NUMBER
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string
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default "Cubieboard A10"
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config MAX_CPUS
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int
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default 1
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config DRAM_SIZE_MB
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int
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default 1024
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config UART_FOR_CONSOLE
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int
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default 0
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endif # BOARD_CUBIETECH_CUBIEBOARD
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@ -1,2 +0,0 @@
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config BOARD_CUBIETECH_CUBIEBOARD
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bool "Cubieboard"
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@ -1,6 +0,0 @@
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bootblock-y += bootblock.c
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romstage-y += romstage.c
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bootblock-y += memlayout.ld
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romstage-y += memlayout.ld
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ramstage-y += memlayout.ld
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@ -1 +0,0 @@
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Category: sbc
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@ -1,157 +0,0 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Minimal bootblock for Cubieboard
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* It sets up CPU clock, and enables the bootblock console.
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*/
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#include <device/mmio.h>
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#include <bootblock_common.h>
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#include <console/uart.h>
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#include <delay.h>
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#include <cpu/allwinner/a10/gpio.h>
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#include <cpu/allwinner/a10/clock.h>
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#include <cpu/allwinner/a10/dramc.h>
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#define CPU_AHB_APB0_DEFAULT \
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CPU_CLK_SRC_OSC24M \
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| APB0_DIV_1 \
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| AHB_DIV_2 \
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| AXI_DIV_1
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#define GPH_STATUS_LEDS (1 << 20) | (1 << 21)
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#define GPH_LED1_PIN_NO 21
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#define GPH_LED2_PIN_NO 20
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#define GPB_UART0_FUNC 2
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#define GPB_UART0_PINS ((1 << 22) | (1 << 23))
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#define GPF_SD0_FUNC 2
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#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */
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#define GPH1_SD0_DET_FUNC 5
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static void cubieboard_set_sys_clock(void)
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{
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u32 reg32;
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struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
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/* Switch CPU clock to main oscillator */
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write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT);
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/* Configure the PLL1. The value is the same one used by u-boot
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* P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
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*/
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write32(&ccm->pll1_cfg, 0xa1005000);
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/* FIXME: Delay to wait for PLL to lock */
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u32 wait = 1000;
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while (--wait);
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/* Switch CPU to PLL clock */
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reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
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reg32 &= ~CPU_CLK_SRC_MASK;
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reg32 |= CPU_CLK_SRC_PLL1;
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write32(&ccm->cpu_ahb_apb0_cfg, reg32);
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}
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static void cubieboard_setup_clocks(void)
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{
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struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
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cubieboard_set_sys_clock();
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/* Configure the clock source for APB1. This drives our UART */
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write32(&ccm->apb1_clk_div_cfg,
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APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0));
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/* Configure the clock for SD0 */
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write32(&ccm->sd0_clk_cfg,
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SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1));
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/* Enable clock to SD0 */
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a1x_periph_clock_enable(A1X_CLKEN_MMC0);
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}
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static void cubieboard_setup_gpios(void)
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{
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/* Mux Status LED pins */
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gpio_set_multipin_func(GPH, GPH_STATUS_LEDS, GPIO_PIN_FUNC_OUTPUT);
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/* Turn on green LED to let user know we're executing coreboot code */
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gpio_set(GPH, GPH_LED2_PIN_NO);
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/* Mux UART pins */
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gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC);
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/* Mux SD pins */
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gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC);
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gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC);
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}
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static void cubieboard_enable_uart(void)
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{
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a1x_periph_clock_enable(A1X_CLKEN_UART0);
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}
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static void cubieboard_raminit(void)
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{
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struct dram_para dram_para = {
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.clock = 480,
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.type = 3,
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.rank_num = 1,
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.density = 4096,
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.io_width = 16,
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.bus_width = 32,
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.cas = 6,
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.zq = 123,
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.odt_en = 0,
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.size = 1024,
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.tpr0 = 0x30926692,
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.tpr1 = 0x1090,
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.tpr2 = 0x1a0c8,
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.tpr3 = 0,
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.tpr4 = 0,
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.tpr5 = 0,
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.emr1 = 0,
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.emr2 = 0,
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.emr3 = 0,
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};
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dramc_init(&dram_para);
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/* FIXME: ram_check does not compile for ARM,
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* and we didn't init console yet
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*/
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////void *const test_base = (void *)A1X_DRAM_BASE;
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////ram_check((u32)test_base, (u32)test_base + 0x1000);
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}
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void bootblock_mainboard_early_init(void)
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{
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/* A10 Timer init uses the 24MHz clock, not PLLs, so we can init it very
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* early on to get udelay, which is used almost everywhere else.
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*/
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init_timer();
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cubieboard_setup_clocks();
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cubieboard_setup_gpios();
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cubieboard_enable_uart();
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}
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void bootblock_mainboard_init(void)
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{
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cubieboard_raminit();
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}
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chip cpu/allwinner/a10
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device cpu_cluster 0 on end
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chip drivers/xpowers/axp209 # AXP209 is on I2C 0
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device i2c 0x34 on end
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register "dcdc2_voltage_mv" = "1400" # Vcore
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register "dcdc3_voltage_mv" = "1250" # DLL Vdd
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register "ldo2_voltage_mv" = "3000" # AVCC
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register "ldo3_voltage_mv" = "2800" # NC?
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register "ldo4_voltage_mv" = "2800" # CSI1-IO-2V8
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end
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end
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <memlayout.h>
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#include <arch/header.ld>
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SECTIONS
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{
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SRAM_START(0x0)
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/* eGON.BT0: 32 bytes */
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BOOTBLOCK(0x20, 0x5fa0)
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STACK(0x6000, 8K)
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SRAM_END(0x8000)
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DRAM_START(0x40000000)
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RAMSTAGE(0x40000000, 16M)
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ROMSTAGE(0x41000000, 108K)
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/* TODO: Implement MMU support and move TTB to a better location. */
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TTB(0x42000000, 16K)
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License, or (at your
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* option) any later version.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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/*
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* Basic romstage for Cubieboard
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*
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* Set up system voltages, then increase the CPU clock, before turning control
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* to ramstage. The CPU VDD needs to be properly set before it can run at full
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* speed. Setting the CPU at full speed helps lzma-decompress ramstage a lot
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* faster.
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*/
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#include <console/console.h>
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#include <cpu/allwinner/a10/clock.h>
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#include <cpu/allwinner/a10/gpio.h>
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#include <cpu/allwinner/a10/twi.h>
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#include <program_loading.h>
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#include <device/device.h>
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#include <drivers/xpowers/axp209/axp209.h>
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#include <drivers/xpowers/axp209/chip.h>
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#include <types.h>
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#define GPB_TWI0_FUNC 2
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#define GPB_TWI0_PINS ((1 << 0) | (1 << 1))
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#define AXP209_BUS 0
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static enum cb_err cubieboard_setup_power(void)
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{
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enum cb_err err;
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const struct device * pmu;
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const struct drivers_xpowers_axp209_config *cfg;
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/* Find the AXP209 in devicetree */
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pmu = dev_find_slot_on_smbus(AXP209_BUS, AXP209_I2C_ADDR);
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if (!pmu) {
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printk(BIOS_ERR, "AXP209 not found in devicetree.cb\n");
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return CB_ERR;
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}
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cfg = pmu->chip_info;
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/* Mux TWI0 pins */
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gpio_set_multipin_func(GPB, GPB_TWI0_PINS, GPB_TWI0_FUNC);
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/* Enable TWI0 */
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a1x_periph_clock_enable(A1X_CLKEN_TWI0);
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a1x_twi_init(AXP209_BUS, 400000);
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if ((err = axp209_init(AXP209_BUS)) != CB_SUCCESS) {
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printk(BIOS_ERR, "PMU initialization failed\n");
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return err;
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}
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if ((err = axp209_set_voltages(AXP209_BUS, cfg)) != CB_SUCCESS) {
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printk(BIOS_WARNING, "Power setup incomplete: "
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"CPU may hang when increasing clock\n");
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return err;
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}
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printk(BIOS_SPEW, "VDD CPU (DCDC2): %imv\n", cfg->dcdc2_voltage_mv);
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printk(BIOS_SPEW, "VDD DLL (DCDC3): %imv\n", cfg->dcdc3_voltage_mv);
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printk(BIOS_SPEW, "AVCC (LDO2) : %imv\n", cfg->ldo2_voltage_mv);
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printk(BIOS_SPEW, "CSI1-IO (LDO4) : %imv\n", cfg->ldo4_voltage_mv);
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printk(BIOS_SPEW, "(LDO3) : %imv\n", cfg->ldo3_voltage_mv);
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return CB_SUCCESS;
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}
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void main(void)
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{
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enum cb_err err;
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console_init();
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/* Configure power rails */
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err = cubieboard_setup_power();
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if (err == CB_SUCCESS) {
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/* TODO: Get this clock from devicetree.cb */
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a1x_set_cpu_clock(1008);
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} else {
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/* cubieboard_setup_power() prints more details */
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printk(BIOS_WARNING, "Will run CPU at reduced speed\n");
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a1x_set_cpu_clock(384);
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}
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run_ramstage();
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}
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