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mb/cubietech/cubieboard: Remove board 

The Allwinner code was never completed and lacks a driver to load
romstage from the bootblock.

Change-Id: I12e9d7213ce61ab757e9317a63299d5d82e69acb
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33132
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Arthur Heymans 2019-05-30 22:40:20 +02:00 committed by Patrick Georgi
parent 2e92adce77
commit 041200fae3
10 changed files with 0 additions and 362 deletions
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17
src/mainboard/cubietech/Kconfig
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@ -1,17 +0,0 @@
if VENDOR_CUBIETECH
# Auto select common options
choice
prompt "Mainboard model"
source "src/mainboard/cubietech/*/Kconfig.name"
endchoice
source "src/mainboard/cubietech/*/Kconfig"
config MAINBOARD_VENDOR
string
default "Cubietech"
endif # VENDOR_CUBIETECH

2
src/mainboard/cubietech/Kconfig.name
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config VENDOR_CUBIETECH
bool "Cubietech"

30
src/mainboard/cubietech/cubieboard/Kconfig
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@ -1,30 +0,0 @@
if BOARD_CUBIETECH_CUBIEBOARD
config BOARD_SPECIFIC_OPTIONS
def_bool y
select CPU_ALLWINNER_A10
select BOARD_ROMSIZE_KB_4096
select DRIVER_XPOWERS_AXP209
select MISSING_BOARD_RESET
config MAINBOARD_DIR
string
default cubietech/cubieboard
config MAINBOARD_PART_NUMBER
string
default "Cubieboard A10"
config MAX_CPUS
int
default 1
config DRAM_SIZE_MB
int
default 1024
config UART_FOR_CONSOLE
int
default 0
endif # BOARD_CUBIETECH_CUBIEBOARD

2
src/mainboard/cubietech/cubieboard/Kconfig.name
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config BOARD_CUBIETECH_CUBIEBOARD
bool "Cubieboard"

6
src/mainboard/cubietech/cubieboard/Makefile.inc
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@ -1,6 +0,0 @@
bootblock-y += bootblock.c
romstage-y += romstage.c
bootblock-y += memlayout.ld
romstage-y += memlayout.ld
ramstage-y += memlayout.ld

1
src/mainboard/cubietech/cubieboard/board_info.txt
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@ -1 +0,0 @@
Category: sbc

157
src/mainboard/cubietech/cubieboard/bootblock.c
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@ -1,157 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Minimal bootblock for Cubieboard
* It sets up CPU clock, and enables the bootblock console.
*/
#include <device/mmio.h>
#include <bootblock_common.h>
#include <console/uart.h>
#include <delay.h>
#include <cpu/allwinner/a10/gpio.h>
#include <cpu/allwinner/a10/clock.h>
#include <cpu/allwinner/a10/dramc.h>
#define CPU_AHB_APB0_DEFAULT \
CPU_CLK_SRC_OSC24M \
| APB0_DIV_1 \
| AHB_DIV_2 \
| AXI_DIV_1
#define GPH_STATUS_LEDS (1 << 20) | (1 << 21)
#define GPH_LED1_PIN_NO 21
#define GPH_LED2_PIN_NO 20
#define GPB_UART0_FUNC 2
#define GPB_UART0_PINS ((1 << 22) | (1 << 23))
#define GPF_SD0_FUNC 2
#define GPF_SD0_PINS 0x3f /* PF0 thru PF5 */
#define GPH1_SD0_DET_FUNC 5
static void cubieboard_set_sys_clock(void)
{
u32 reg32;
struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
/* Switch CPU clock to main oscillator */
write32(&ccm->cpu_ahb_apb0_cfg, CPU_AHB_APB0_DEFAULT);
/* Configure the PLL1. The value is the same one used by u-boot
* P = 1, N = 16, K = 1, M = 1 --> Output = 384 MHz
*/
write32(&ccm->pll1_cfg, 0xa1005000);
/* FIXME: Delay to wait for PLL to lock */
u32 wait = 1000;
while (--wait);
/* Switch CPU to PLL clock */
reg32 = read32(&ccm->cpu_ahb_apb0_cfg);
reg32 &= ~CPU_CLK_SRC_MASK;
reg32 |= CPU_CLK_SRC_PLL1;
write32(&ccm->cpu_ahb_apb0_cfg, reg32);
}
static void cubieboard_setup_clocks(void)
{
struct a10_ccm *ccm = (void *)A1X_CCM_BASE;
cubieboard_set_sys_clock();
/* Configure the clock source for APB1. This drives our UART */
write32(&ccm->apb1_clk_div_cfg,
APB1_CLK_SRC_OSC24M | APB1_RAT_N(0) | APB1_RAT_M(0));
/* Configure the clock for SD0 */
write32(&ccm->sd0_clk_cfg,
SDx_CLK_GATE | SDx_CLK_SRC_OSC24M | SDx_RAT_EXP_N(0) | SDx_RAT_M(1));
/* Enable clock to SD0 */
a1x_periph_clock_enable(A1X_CLKEN_MMC0);
}
static void cubieboard_setup_gpios(void)
{
/* Mux Status LED pins */
gpio_set_multipin_func(GPH, GPH_STATUS_LEDS, GPIO_PIN_FUNC_OUTPUT);
/* Turn on green LED to let user know we're executing coreboot code */
gpio_set(GPH, GPH_LED2_PIN_NO);
/* Mux UART pins */
gpio_set_multipin_func(GPB, GPB_UART0_PINS, GPB_UART0_FUNC);
/* Mux SD pins */
gpio_set_multipin_func(GPF, GPF_SD0_PINS, GPF_SD0_FUNC);
gpio_set_pin_func(GPH, 1, GPH1_SD0_DET_FUNC);
}
static void cubieboard_enable_uart(void)
{
a1x_periph_clock_enable(A1X_CLKEN_UART0);
}
static void cubieboard_raminit(void)
{
struct dram_para dram_para = {
.clock = 480,
.type = 3,
.rank_num = 1,
.density = 4096,
.io_width = 16,
.bus_width = 32,
.cas = 6,
.zq = 123,
.odt_en = 0,
.size = 1024,
.tpr0 = 0x30926692,
.tpr1 = 0x1090,
.tpr2 = 0x1a0c8,
.tpr3 = 0,
.tpr4 = 0,
.tpr5 = 0,
.emr1 = 0,
.emr2 = 0,
.emr3 = 0,
};
dramc_init(&dram_para);
/* FIXME: ram_check does not compile for ARM,
* and we didn't init console yet
*/
////void *const test_base = (void *)A1X_DRAM_BASE;
////ram_check((u32)test_base, (u32)test_base + 0x1000);
}
void bootblock_mainboard_early_init(void)
{
/* A10 Timer init uses the 24MHz clock, not PLLs, so we can init it very
* early on to get udelay, which is used almost everywhere else.
*/
init_timer();
cubieboard_setup_clocks();
cubieboard_setup_gpios();
cubieboard_enable_uart();
}
void bootblock_mainboard_init(void)
{
cubieboard_raminit();
}

12
src/mainboard/cubietech/cubieboard/devicetree.cb
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@ -1,12 +0,0 @@
chip cpu/allwinner/a10
device cpu_cluster 0 on end
chip drivers/xpowers/axp209 # AXP209 is on I2C 0
device i2c 0x34 on end
register "dcdc2_voltage_mv" = "1400" # Vcore
register "dcdc3_voltage_mv" = "1250" # DLL Vdd
register "ldo2_voltage_mv" = "3000" # AVCC
register "ldo3_voltage_mv" = "2800" # NC?
register "ldo4_voltage_mv" = "2800" # CSI1-IO-2V8
end
end

34
src/mainboard/cubietech/cubieboard/memlayout.ld
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@ -1,34 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
#include <memlayout.h>
#include <arch/header.ld>
SECTIONS
{
SRAM_START(0x0)
/* eGON.BT0: 32 bytes */
BOOTBLOCK(0x20, 0x5fa0)
STACK(0x6000, 8K)
SRAM_END(0x8000)
DRAM_START(0x40000000)
RAMSTAGE(0x40000000, 16M)
ROMSTAGE(0x41000000, 108K)
/* TODO: Implement MMU support and move TTB to a better location. */
TTB(0x42000000, 16K)
}

101
src/mainboard/cubietech/cubieboard/romstage.c
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@ -1,101 +0,0 @@
/*
* This file is part of the coreboot project.
*
* Copyright (C) 2013 Alexandru Gagniuc <mr.nuke.me@gmail.com>
*
* This program is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; version 2 of the License, or (at your
* option) any later version.
*
* This program is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*/
/*
* Basic romstage for Cubieboard
*
* Set up system voltages, then increase the CPU clock, before turning control
* to ramstage. The CPU VDD needs to be properly set before it can run at full
* speed. Setting the CPU at full speed helps lzma-decompress ramstage a lot
* faster.
*/
#include <console/console.h>
#include <cpu/allwinner/a10/clock.h>
#include <cpu/allwinner/a10/gpio.h>
#include <cpu/allwinner/a10/twi.h>
#include <program_loading.h>
#include <device/device.h>
#include <drivers/xpowers/axp209/axp209.h>
#include <drivers/xpowers/axp209/chip.h>
#include <types.h>
#define GPB_TWI0_FUNC 2
#define GPB_TWI0_PINS ((1 << 0) | (1 << 1))
#define AXP209_BUS 0
static enum cb_err cubieboard_setup_power(void)
{
enum cb_err err;
const struct device * pmu;
const struct drivers_xpowers_axp209_config *cfg;
/* Find the AXP209 in devicetree */
pmu = dev_find_slot_on_smbus(AXP209_BUS, AXP209_I2C_ADDR);
if (!pmu) {
printk(BIOS_ERR, "AXP209 not found in devicetree.cb\n");
return CB_ERR;
}
cfg = pmu->chip_info;
/* Mux TWI0 pins */
gpio_set_multipin_func(GPB, GPB_TWI0_PINS, GPB_TWI0_FUNC);
/* Enable TWI0 */
a1x_periph_clock_enable(A1X_CLKEN_TWI0);
a1x_twi_init(AXP209_BUS, 400000);
if ((err = axp209_init(AXP209_BUS)) != CB_SUCCESS) {
printk(BIOS_ERR, "PMU initialization failed\n");
return err;
}
if ((err = axp209_set_voltages(AXP209_BUS, cfg)) != CB_SUCCESS) {
printk(BIOS_WARNING, "Power setup incomplete: "
"CPU may hang when increasing clock\n");
return err;
}
printk(BIOS_SPEW, "VDD CPU (DCDC2): %imv\n", cfg->dcdc2_voltage_mv);
printk(BIOS_SPEW, "VDD DLL (DCDC3): %imv\n", cfg->dcdc3_voltage_mv);
printk(BIOS_SPEW, "AVCC (LDO2) : %imv\n", cfg->ldo2_voltage_mv);
printk(BIOS_SPEW, "CSI1-IO (LDO4) : %imv\n", cfg->ldo4_voltage_mv);
printk(BIOS_SPEW, "(LDO3) : %imv\n", cfg->ldo3_voltage_mv);
return CB_SUCCESS;
}
void main(void)
{
enum cb_err err;
console_init();
/* Configure power rails */
err = cubieboard_setup_power();
if (err == CB_SUCCESS) {
/* TODO: Get this clock from devicetree.cb */
a1x_set_cpu_clock(1008);
} else {
/* cubieboard_setup_power() prints more details */
printk(BIOS_WARNING, "Will run CPU at reduced speed\n");
a1x_set_cpu_clock(384);
}
run_ramstage();
}