soc/amd/morgana: Update pci int defs
Update pci int defs per preview of next ppr after rev 1.52, #57396 Update birman and mayan mainboards to remove deleted PIRQs. Signed-off-by: Fred Reitberger <reitbergerfred@gmail.com> Change-Id: I10e13784761f0b9245f0ca10e3cd07d396ec4224 Reviewed-on: https://review.coreboot.org/c/coreboot/+/70379 Reviewed-by: Felix Held <felix-coreboot@felixheld.de> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
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@ -33,9 +33,7 @@ static const struct fch_irq_routing fch_irq_map[] = {
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{ PIRQ_H, 14, PIRQ_NC },
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{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
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{ PIRQ_SD, PIRQ_NC, PIRQ_NC },
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{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
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{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
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{ PIRQ_GPIO, 11, 11 },
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{ PIRQ_I2C0, 10, 10 },
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{ PIRQ_I2C1, 7, 7 },
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@ -33,9 +33,7 @@ static const struct fch_irq_routing fch_irq_map[] = {
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{ PIRQ_H, 14, PIRQ_NC },
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{ PIRQ_SCI, ACPI_SCI_IRQ, ACPI_SCI_IRQ },
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{ PIRQ_SD, PIRQ_NC, PIRQ_NC },
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{ PIRQ_SDIO, PIRQ_NC, PIRQ_NC },
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{ PIRQ_EMMC, PIRQ_NC, PIRQ_NC },
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{ PIRQ_GPIO, 11, 11 },
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{ PIRQ_I2C0, 10, 10 },
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{ PIRQ_I2C1, 7, 7 },
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@ -22,10 +22,9 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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PIRG, 0x00000008, /* Index 6: INTG */
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PIRH, 0x00000008, /* Index 7: INTH */
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Offset (0x43),
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PMMC, 0x00000008, /* Index 0x43: eMMC */
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Offset (0x62),
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Offset (0x60),
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PGSC, 0x00000008, /* Index 0x60: GEventSci */
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PGSM, 0x00000008, /* Index 0x61: GEventSmi */
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PGPI, 0x00000008, /* Index 0x62: GPIO */
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Offset (0x70),
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@ -35,7 +34,8 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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PI23, 0x00000008, /* Index 0x73: I2C3 */
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PUA0, 0x00000008, /* Index 0x74: UART0 */
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PUA1, 0x00000008, /* Index 0x75: UART1 */
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PI24, 0x00000008, /* Index 0x76: I2C4 */
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Offset (0x77),
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PUA4, 0x00000008, /* Index 0x77: UART4 */
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PUA2, 0x00000008, /* Index 0x78: UART2 */
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PUA3, 0x00000008, /* Index 0x79: UART3 */
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@ -51,10 +51,9 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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IORG, 0x00000008, /* Index 0x86: INTG */
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IORH, 0x00000008, /* Index 0x87: INTH */
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Offset (0xC3),
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IMMC, 0x00000008, /* Index 0xC3: eMMC */
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Offset (0xE2),
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Offset (0xE0),
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IGSC, 0x00000008, /* Index 0xE0: GEventSci */
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IGSM, 0x00000008, /* Index 0xE1: GEventSmi */
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IGPI, 0x00000008, /* Index 0xE2: GPIO */
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Offset (0xF0),
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@ -64,7 +63,8 @@ IndexField(PRQI, PRQD, ByteAcc, NoLock, Preserve) {
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II23, 0x00000008, /* Index 0xF3: I2C3 */
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IUA0, 0x00000008, /* Index 0xF4: UART0 */
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IUA1, 0x00000008, /* Index 0xF5: UART1 */
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II24, 0x00000008, /* Index 0xF6: I2C4 */
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Offset (0xF7),
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IUA4, 0x00000008, /* Index 0xF7: UART4 */
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IUA2, 0x00000008, /* Index 0xF8: UART2 */
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IUA3, 0x00000008, /* Index 0xF9: UART3 */
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@ -46,17 +46,13 @@ const static struct irq_idx_name irq_association[] = {
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{ PIRQ_SMBUS, "SMBUS" },
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{ PIRQ_ASF, "ASF" },
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{ PIRQ_PMON, "PerMon" },
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{ PIRQ_SD, "SD" },
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{ PIRQ_SDIO, "SDIO" },
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{ PIRQ_CIR, "CIR" },
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{ PIRQ_GPIOA, "GPIOa" },
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{ PIRQ_GPIOB, "GPIOb" },
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{ PIRQ_GPIOC, "GPIOc" },
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{ PIRQ_EMMC, "eMMC" },
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{ PIRQ_GPP0, "GPP0" },
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{ PIRQ_GPP1, "GPP1" },
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{ PIRQ_GPP2, "GPP2" },
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{ PIRQ_GPP3, "GPP3" },
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{ PIRQ_GSCI, "GEventSci" },
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{ PIRQ_GSMI, "GEventSmi" },
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{ PIRQ_GPIO, "GPIO" },
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{ PIRQ_I2C0, "I2C0" },
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{ PIRQ_I2C1, "I2C1" },
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@ -64,7 +60,6 @@ const static struct irq_idx_name irq_association[] = {
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{ PIRQ_I2C3, "I2C3" },
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{ PIRQ_UART0, "UART0" },
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{ PIRQ_UART1, "UART1" },
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{ PIRQ_I2C4, "I2C4" },
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{ PIRQ_UART4, "UART4" },
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{ PIRQ_UART2, "UART2" },
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{ PIRQ_UART3, "UART3" },
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@ -1,7 +1,5 @@
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/* SPDX-License-Identifier: GPL-2.0-only */
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/* TODO: Update for Morgana */
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#ifndef AMD_MORGANA_AMD_PCI_INT_DEFS_H
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#define AMD_MORGANA_AMD_PCI_INT_DEFS_H
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@ -32,22 +30,16 @@
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#define PIRQ_ASF 0x12 /* ASF */
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/* 0x13-0x15 reserved */
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#define PIRQ_PMON 0x16 /* Performance Monitor */
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#define PIRQ_SD 0x17 /* SD */
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/* 0x18-0x19 reserved */
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/* 0x17-0x19 reserved */
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#define PIRQ_SDIO 0x1a /* SDIO */
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/* 0x1b-0x1f reserved */
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#define PIRQ_CIR 0x20 /* CIR, no IRQ connected */
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#define PIRQ_GPIOA 0x21 /* GPIOa from PAD_FANIN0 */
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#define PIRQ_GPIOB 0x22 /* GPIOb from PAD_FANOUT0 */
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#define PIRQ_GPIOC 0x23 /* GPIOc no IRQ connected */
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/* 0x24-0x42 reserved */
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#define PIRQ_EMMC 0x43 /* eMMC */
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/* 0x44-0x4f reserved */
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#define PIRQ_GPP0 0x50 /* GPPInt0 */
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#define PIRQ_GPP1 0x51 /* GPPInt1 */
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#define PIRQ_GPP2 0x52 /* GPPInt2 */
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#define PIRQ_GPP3 0x53 /* GPPInt3 */
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/* 0x54-0x61 reserved */
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/* 0x24-0x5f reserved */
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#define PIRQ_GSCI 0x60 /* GEventSci Interrupt */
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#define PIRQ_GSMI 0x61 /* GEventSmi Interrupt */
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#define PIRQ_GPIO 0x62 /* GPIO Controller Interrupt */
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/* 0x63-0x6f reserved */
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#define PIRQ_I2C0 0x70 /* I2C0 */
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@ -56,7 +48,7 @@
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#define PIRQ_I2C3 0x73 /* I2C3 */
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#define PIRQ_UART0 0x74 /* UART0 */
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#define PIRQ_UART1 0x75 /* UART1 */
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#define PIRQ_I2C4 0x76 /* I2C4 */
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/* 0x76 reserved */
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#define PIRQ_UART4 0x77 /* UART4 */
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#define PIRQ_UART2 0x78 /* UART2 */
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#define PIRQ_UART3 0x79 /* UART3 */
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