mb/google/octopus: add support for fetching DRAM part number from CBI

Add 3 new Kconfig options:
DRAM_PART_NUM_IN_CBI
DRAM_PART_NUM_ALWAYS_IN_CBI
DRAM_PART_IN_CBI_BOARD_ID_MIN

These control whether to 1. attempt to use CBI at all 2. always use cbi
and 3. conditionally use cbi based on board id. The intent is that the
MIN variant would be used for the tranisition period then cut over to
ALWAYS after full transition. Since multiple OEMs have different
schedules these options are there to bridge the gap. yorp. bip, and
octopus build targets would never flip DRAM_PART_NUM_IN_CBI, but in case
someone does the MIN values are 255 to always take the old path.

BUG=b:112203105
TEST=Set correct part number on phaser during testing.

Change-Id: If9a0102806d78e89330b42aa6947d503a8a2deac
Signed-off-by: Aaron Durbin <adurbin@chromium.org>
Reviewed-on: https://review.coreboot.org/27946
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>

src/mainboard/google/octopus/Kconfig

@@ -100,4 +100,22 @@ config TPM_TIS_ACPI_INTERRUPT
 	int
 	default 63 # GPE0_DW1_31 (GPIO_63)
 
+config DRAM_PART_NUM_IN_CBI
+	bool
+
+config DRAM_PART_NUM_ALWAYS_IN_CBI
+	bool
+	depends on DRAM_PART_NUM_IN_CBI
+
+config DRAM_PART_IN_CBI_BOARD_ID_MIN
+	int
+	depends on DRAM_PART_NUM_IN_CBI && !DRAM_PART_NUM_ALWAYS_IN_CBI
+	default 255 if BOARD_GOOGLE_YORP
+	default 255 if BOARD_GOOGLE_BIP
+	default 9 if BOARD_GOOGLE_PHASER
+	default 9 if BOARD_GOOGLE_FLEEX
+	default 9 if BOARD_GOOGLE_BOBBA
+	default 9 if BOARD_GOOGLE_MEEP
+	default 255 if BOARD_GOOGLE_OCTOPUS
+
 endif # BOARD_GOOGLE_OCTOPUS

src/mainboard/google/octopus/romstage.c

@@ -15,6 +15,8 @@
 #include <string.h>
 #include <baseboard/variants.h>
 #include <boardid.h>
+#include <console/console.h>
+#include <ec/google/chromeec/ec.h>
 #include <soc/meminit.h>
 #include <soc/romstage.h>
 
@@ -24,7 +26,34 @@ void mainboard_memory_init_params(FSPM_UPD *memupd)
 		variant_lpddr4_config(), variant_memory_sku());
 }
 
-void mainboard_save_dimm_info(void)
+static void save_dimm_info_by_sku_config(void)
 {
 	save_lpddr4_dimm_info(variant_lpddr4_config(), variant_memory_sku());
 }
+
+void mainboard_save_dimm_info(void)
+{
+	char part_num_store[32];
+	const char *part_num = NULL;
+
+	if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_IN_CBI)) {
+		save_dimm_info_by_sku_config();
+		return;
+	}
+
+	if (!IS_ENABLED(CONFIG_DRAM_PART_NUM_ALWAYS_IN_CBI)) {
+		/* Fall back on part numbers encoded in lp4cfg array. */
+		if (board_id() < CONFIG_DRAM_PART_IN_CBI_BOARD_ID_MIN) {
+			save_dimm_info_by_sku_config();
+			return;
+		}
+	}
+
+	if (google_chromeec_cbi_get_dram_part_num(&part_num_store[0],
+			ARRAY_SIZE(part_num_store)) < 0)
+		printk(BIOS_ERR, "ERROR: Couldn't obtain DRAM part number from CBI\n");
+	else
+		part_num = &part_num_store[0];
+
+	save_lpddr4_dimm_info_part_num(part_num);
+}