resolving conflict with Ron's work
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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a5ce2341ec
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042f0430d3
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@ -62,11 +62,11 @@ end
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makerule ./auto.E
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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makerule ./auto.inc
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depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
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action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
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end
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##
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@ -18,6 +18,12 @@
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#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
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#include "southbridge/amd/cs5535/cs5535_early_setup.c"
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static inline int spd_read_byte(unsigned device, unsigned address)
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{
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return smbus_read_byte(device, address);
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}
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#include "northbridge/amd/gx2/raminit.h"
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static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
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@ -33,10 +39,9 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
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msr = rdmsr(0x20000019);
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msr.hi = 0x18000108;
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msr.lo = 0x696332a3;
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wrmsr(0x20000019, msr);
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wrmsr(0x20000019, msr);
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}
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#include "northbridge/amd/gx2/raminit.c"
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#include "sdram/generic_sdram.c"
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@ -86,33 +86,38 @@ static const unsigned char fbdiv2plldiv[] = {
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49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
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};
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#if 1
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static void get_memory_speed(void)
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static const unsigned char pci33_sdr_crt [] = {
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/* FbDIV, VDIV, MDIV CPU/GeodeLink */
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12, 2, 4, // 200/100
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16, 2, 4, // 266/133
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18, 2, 5, // 300/120
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20, 2, 5, // 333/133
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22, 2, 6, // 366/122
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24, 2, 6, // 400/133
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26, 2, 6 // 433/144
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};
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static const unsigned char pci33_ddr_crt [] = {
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/* FbDIV, VDIV, MDIV CPU/GeodeLink */
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12, 2, 3, // 200/133
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16, 2, 3, // 266/177
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18, 2, 3, // 300/200
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20, 2, 3, // 333/222
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22, 2, 3, // 366/244
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24, 2, 3, // 400/266
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26, 2, 3 // 433/289
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};
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static unsigned int get_memory_speed(void)
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{
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unsigned char val;
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unsigned char val, hi, lo;
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val = do_smbus_read_byte(0x6000, 0xA0, 0);
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print_debug("SPD byte ");
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print_debug_hex8(0);
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print_debug(" = ");
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print_debug_hex8(val);
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print_debug("\r\n");
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val = spd_read_byte(0xA0, 9);
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hi = (val >> 4) & 0x0f;
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lo = val & 0x0f;
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val = do_smbus_read_byte(0x6000, 0xA0, 1);
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print_debug("SPD byte ");
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print_debug_hex8(1);
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print_debug(" = ");
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print_debug_hex8(val);
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print_debug("\r\n");
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val = do_smbus_read_byte(0x6000, 0xA0, 2);
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print_debug("SPD byte ");
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print_debug_hex8(2);
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print_debug(" = ");
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print_debug_hex8(val);
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print_debug("\r\n");
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return 20000/(hi*10 + lo);
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}
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#endif
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static void pll_reset(void)
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{
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@ -125,14 +130,10 @@ static void pll_reset(void)
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print_debug("Cpu core is ");
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print_debug_hex32(cpu_core);
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print_debug("\n");
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//get_memory_speed();
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//msr = rdmsr(GLCP_SYS_RSTPLL);
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msr = rdmsr(0x4c000014);
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print_debug("4c000014 is ");
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print_debug_hex32(msr.hi); print_debug(":"); print_debug_hex32(msr.lo); print_debug("\n");
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if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
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print_debug("disable PLL bypass\n\r");
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msr = rdmsr(GLCP_SYS_RSTPLL);
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if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
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#if 0
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msr.hi = PLLMSRhi;
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msr.lo = PLLMSRlo;
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wrmsr(GLCP_SYS_RSTPLL, msr);
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@ -144,6 +145,10 @@ static void pll_reset(void)
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msr.lo |= PLLMSRlo2;
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wrmsr(GLCP_SYS_RSTPLL,msr);
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print_debug("should not be here\n\r");
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#endif
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print_err("shit");
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while (1)
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;
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}
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if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
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@ -152,25 +157,16 @@ static void pll_reset(void)
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return;
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}
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print_debug("prgramming PLL\n\r");
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/* get the sysref clock rate */
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vdiv = (msr.hi >> GLCP_SYS_RSTPLL_VDIV_SHIFT) & 0x07;
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vdiv += 2;
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fbdiv = (msr.hi >> GLCP_SYS_RSTPLL_FBDIV_SHIFT) & 0x3f;
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fbdiv = fbdiv2plldiv[fbdiv];
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spll_raw = cpu_core * vdiv;
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sysref = spll_raw / fbdiv;
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print_debug("SYSREF/PCI Clock ");
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print_debug_hex32(sysref);
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print_debug("\n\r");
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/* get target memory rate by SPD */
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//gliu = get_memory_speed();
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//get_memory_speed();
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//print_debug("Target Memory Clock ");
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//print_debug_hex32(gliu);
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//print_debug("\n\r");
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msr.hi = 0x00000019;
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msr.lo = 0x06de0378;
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@ -4,7 +4,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
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{
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}
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#if 0
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static void sdram_set_spd_registers(const struct mem_controller *ctrl)
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{
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msr_t mst;
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unsigned char val;
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/* get module banks per dimm, SPD byte 5 */
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val = spd_read_byte(0xA0, 5);
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if (val < 1 || val > 2)
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print_err("Module banks per dimm");
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}
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#endif
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/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
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* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
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static void sdram_enable(int controllers, const struct mem_controller *ctrl)
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@ -113,6 +113,5 @@ static int cs5535_early_setup(void)
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cs5535_setup_cis_mode();
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print_debug("Setup smbus\r\n");
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cs5535_enable_smbus();
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//get_memory_speed();
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dummy();
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}
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@ -7,6 +7,7 @@ static int cs5535_enable_smbus(void)
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{
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unsigned char val;
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/* reset SMBUS controller */
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outb(0, SMBUS_IO_BASE + SMB_CTRL2);
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/* Set SCL freq and enable SMB controller */
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@ -18,24 +19,11 @@ static int cs5535_enable_smbus(void)
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val = inb(SMBUS_IO_BASE + SMB_ADD);
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val |= (0xEF | SMB_ADD_SAEN);
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outb(val, SMBUS_IO_BASE + SMB_ADD);
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}
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#if 0
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print_debug("SMBUS registers ");
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print_debug_hex8(inb(SMBUS_IO_BASE));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 1));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 2));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 3));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 4));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 5));
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print_debug(" ");
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print_debug_hex8(inb(SMBUS_IO_BASE + 6));
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print_debug("\n\r");
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#endif
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1);
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}
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#if 0
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@ -49,10 +37,6 @@ static int smbus_send_byte(unsigned device, unsigned char val)
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return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
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}
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static int smbus_read_byte(unsigned device, unsigned address)
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{
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return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
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}
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static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
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{
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@ -43,6 +43,8 @@
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#define SMBUS_TIMEOUT (100*1000*10)
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#define SMBUS_STATUS_MASK 0xfbff
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#define SMBUS_IO_BASE 0x6000
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static void smbus_delay(void)
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{
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outb(0x80, 0x80);
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@ -75,6 +77,29 @@ static int smbus_start_condition(unsigned smbus_io_base)
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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static int smbus_check_stop_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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unsigned long loops;
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loops = SMBUS_TIMEOUT;
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/* check for SDA status */
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do {
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smbus_delay();
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val = inw(smbus_io_base + SMB_CTRL1);
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if ((val & SMB_CTRL1_STOP) == 0) {
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break;
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}
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} while(--loops);
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return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
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}
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static int smbus_stop_condition(unsigned smbus_io_base)
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{
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unsigned char val;
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
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}
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static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
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{
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unsigned char val;
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/* check for bus conflict and NACK */
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val = inb(smbus_io_base + SMB_STS);
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if ( ((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0))
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if (((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0))
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return SMBUS_ERROR;
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/* check for SDA status */
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/* check for bus conflict and NACK */
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val = inb(smbus_io_base + SMB_STS);
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if ( ((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0))
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if (((val & SMB_STS_BER) != 0) ||
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((val & SMB_STS_NEGACK) != 0))
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return SMBUS_ERROR;
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/* check for SDA status */
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static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
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{
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unsigned char val;
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unsigned char val, val1;
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if (smbus_start_condition(smbus_io_base) < 0)
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print_debug("smbus error 1");
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smbus_check_stop_condition(smbus_io_base);
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if (smbus_send_slave_address(smbus_io_base, device) < 0)
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print_debug("smbus error 2");
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smbus_start_condition(smbus_io_base);
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if (smbus_send_command(smbus_io_base, address) < 0)
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print_debug("smbus error 3");
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smbus_send_slave_address(smbus_io_base, device);
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if (smbus_start_condition(smbus_io_base) < 0)
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print_debug("smbus error 4");
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smbus_send_command(smbus_io_base, address);
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if (smbus_send_slave_address(smbus_io_base, device | 0x01))
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print_debug("smbus error 5");
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smbus_start_condition(smbus_io_base);
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smbus_send_slave_address(smbus_io_base, device | 0x01);
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/* send NACK to slave */
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val = inb(smbus_io_base + SMB_CTRL1);
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outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
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return inb(smbus_io_base + SMB_SDA);
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val = inb(smbus_io_base + SMB_SDA);
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//smbus_stop_condition(smbus_io_base);
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return val;
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}
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