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resolving conflict with Ron's work 

git-svn-id: svn://svn.coreboot.org/coreboot/trunk@2209 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
Li-Ta Lo 2006-03-17 20:11:38 +00:00
parent a5ce2341ec
commit 042f0430d3
7 changed files with 107 additions and 84 deletions
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4
src/mainboard/amd/rumba/Config.lb
View File

@ -62,11 +62,11 @@ end
makerule ./auto.E
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -E -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
action "./romcc -E -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
makerule ./auto.inc
depends "$(MAINBOARD)/auto.c option_table.h ./romcc"
action "./romcc -mcpu=i386 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
action "./romcc -mcpu=p2 -O -I$(TOP)/src -I. $(CPPFLAGS) $(MAINBOARD)/auto.c -o $@"
end
##

9
src/mainboard/amd/rumba/auto.c
View File

@ -18,6 +18,12 @@
#include "southbridge/amd/cs5535/cs5535_early_smbus.c"
#include "southbridge/amd/cs5535/cs5535_early_setup.c"
static inline int spd_read_byte(unsigned device, unsigned address)
{
return smbus_read_byte(device, address);
}
#include "northbridge/amd/gx2/raminit.h"
static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
@ -34,9 +40,8 @@ static void sdram_set_spd_registers(const struct mem_controller *ctrl) {
msr.hi = 0x18000108;
msr.lo = 0x696332a3;
wrmsr(0x20000019, msr);
}
#include "northbridge/amd/gx2/raminit.c"
#include "sdram/generic_sdram.c"

78
src/northbridge/amd/gx2/pll_reset.c
View File

@ -86,33 +86,38 @@ static const unsigned char fbdiv2plldiv[] = {
49, 40, 19, 59, 32, 54, 35, 0, 41, 60, 55, 0, 61, 0, 0, 0
};
#if 1
static void get_memory_speed(void)
static const unsigned char pci33_sdr_crt [] = {
/* FbDIV, VDIV, MDIV CPU/GeodeLink */
12, 2, 4, // 200/100
16, 2, 4, // 266/133
18, 2, 5, // 300/120
20, 2, 5, // 333/133
22, 2, 6, // 366/122
24, 2, 6, // 400/133
26, 2, 6 // 433/144
};
static const unsigned char pci33_ddr_crt [] = {
/* FbDIV, VDIV, MDIV CPU/GeodeLink */
12, 2, 3, // 200/133
16, 2, 3, // 266/177
18, 2, 3, // 300/200
20, 2, 3, // 333/222
22, 2, 3, // 366/244
24, 2, 3, // 400/266
26, 2, 3 // 433/289
};
static unsigned int get_memory_speed(void)
{
unsigned char val;
unsigned char val, hi, lo;
val = do_smbus_read_byte(0x6000, 0xA0, 0);
print_debug("SPD byte ");
print_debug_hex8(0);
print_debug(" = ");
print_debug_hex8(val);
print_debug("\r\n");
val = spd_read_byte(0xA0, 9);
hi = (val >> 4) & 0x0f;
lo = val & 0x0f;
val = do_smbus_read_byte(0x6000, 0xA0, 1);
print_debug("SPD byte ");
print_debug_hex8(1);
print_debug(" = ");
print_debug_hex8(val);
print_debug("\r\n");
val = do_smbus_read_byte(0x6000, 0xA0, 2);
print_debug("SPD byte ");
print_debug_hex8(2);
print_debug(" = ");
print_debug_hex8(val);
print_debug("\r\n");
return 20000/(hi*10 + lo);
}
#endif
static void pll_reset(void)
{
@ -125,14 +130,10 @@ static void pll_reset(void)
print_debug("Cpu core is ");
print_debug_hex32(cpu_core);
print_debug("\n");
//get_memory_speed();
//msr = rdmsr(GLCP_SYS_RSTPLL);
msr = rdmsr(0x4c000014);
print_debug("4c000014 is ");
print_debug_hex32(msr.hi); print_debug(":"); print_debug_hex32(msr.lo); print_debug("\n");
if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
print_debug("disable PLL bypass\n\r");
msr = rdmsr(GLCP_SYS_RSTPLL);
if (msr.lo & (1 << GLCP_SYS_RSTPLL_BYPASS)) {
#if 0
msr.hi = PLLMSRhi;
msr.lo = PLLMSRlo;
wrmsr(GLCP_SYS_RSTPLL, msr);
@ -144,6 +145,10 @@ static void pll_reset(void)
msr.lo |= PLLMSRlo2;
wrmsr(GLCP_SYS_RSTPLL,msr);
print_debug("should not be here\n\r");
#endif
print_err("shit");
while (1)
;
}
if (msr.lo & GLCP_SYS_RSTPLL_SWFLAGS_MASK) {
@ -152,25 +157,16 @@ static void pll_reset(void)
return;
}
print_debug("prgramming PLL\n\r");
/* get the sysref clock rate */
vdiv = (msr.hi >> GLCP_SYS_RSTPLL_VDIV_SHIFT) & 0x07;
vdiv += 2;
fbdiv = (msr.hi >> GLCP_SYS_RSTPLL_FBDIV_SHIFT) & 0x3f;
fbdiv = fbdiv2plldiv[fbdiv];
spll_raw = cpu_core * vdiv;
sysref = spll_raw / fbdiv;
print_debug("SYSREF/PCI Clock ");
print_debug_hex32(sysref);
print_debug("\n\r");
/* get target memory rate by SPD */
//gliu = get_memory_speed();
//get_memory_speed();
//print_debug("Target Memory Clock ");
//print_debug_hex32(gliu);
//print_debug("\n\r");
msr.hi = 0x00000019;
msr.lo = 0x06de0378;

12
src/northbridge/amd/gx2/raminit.c
View File

@ -4,7 +4,19 @@ static void sdram_set_registers(const struct mem_controller *ctrl)
{
}
#if 0
static void sdram_set_spd_registers(const struct mem_controller *ctrl)
{
msr_t mst;
unsigned char val;
/* get module banks per dimm, SPD byte 5 */
val = spd_read_byte(0xA0, 5);
if (val < 1 || val > 2)
print_err("Module banks per dimm");
}
#endif
/* Section 6.1.3, LX processor databooks, BIOS Initialization Sequence
* Section 4.1.4, GX/CS5535 GeodeROM Porting guide */
static void sdram_enable(int controllers, const struct mem_controller *ctrl)

1
src/southbridge/amd/cs5535/cs5535_early_setup.c
View File

@ -113,6 +113,5 @@ static int cs5535_early_setup(void)
cs5535_setup_cis_mode();
print_debug("Setup smbus\r\n");
cs5535_enable_smbus();
//get_memory_speed();
dummy();
}

26
src/southbridge/amd/cs5535/cs5535_early_smbus.c
View File

@ -7,6 +7,7 @@ static int cs5535_enable_smbus(void)
{
unsigned char val;
/* reset SMBUS controller */
outb(0, SMBUS_IO_BASE + SMB_CTRL2);
/* Set SCL freq and enable SMB controller */
@ -18,24 +19,11 @@ static int cs5535_enable_smbus(void)
val = inb(SMBUS_IO_BASE + SMB_ADD);
val |= (0xEF | SMB_ADD_SAEN);
outb(val, SMBUS_IO_BASE + SMB_ADD);
}
#if 0
print_debug("SMBUS registers ");
print_debug_hex8(inb(SMBUS_IO_BASE));
print_debug(" ");
print_debug_hex8(inb(SMBUS_IO_BASE + 1));
print_debug(" ");
print_debug_hex8(inb(SMBUS_IO_BASE + 2));
print_debug(" ");
print_debug_hex8(inb(SMBUS_IO_BASE + 3));
print_debug(" ");
print_debug_hex8(inb(SMBUS_IO_BASE + 4));
print_debug(" ");
print_debug_hex8(inb(SMBUS_IO_BASE + 5));
print_debug(" ");
print_debug_hex8(inb(SMBUS_IO_BASE + 6));
print_debug("\n\r");
#endif
static int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address-1);
}
#if 0
@ -49,10 +37,6 @@ static int smbus_send_byte(unsigned device, unsigned char val)
return do_smbus_send_byte(SMBUS_IO_BASE, device, val);
}
static int smbus_read_byte(unsigned device, unsigned address)
{
return do_smbus_read_byte(SMBUS_IO_BASE, device, address);
}
static int smbus_write_byte(unsigned device, unsigned address, unsigned char val)
{

55
src/southbridge/amd/cs5535/cs5535_smbus.h
View File

@ -43,6 +43,8 @@
#define SMBUS_TIMEOUT (100*1000*10)
#define SMBUS_STATUS_MASK 0xfbff
#define SMBUS_IO_BASE 0x6000
static void smbus_delay(void)
{
outb(0x80, 0x80);
@ -75,6 +77,29 @@ static int smbus_start_condition(unsigned smbus_io_base)
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static int smbus_check_stop_condition(unsigned smbus_io_base)
{
unsigned char val;
unsigned long loops;
loops = SMBUS_TIMEOUT;
/* check for SDA status */
do {
smbus_delay();
val = inw(smbus_io_base + SMB_CTRL1);
if ((val & SMB_CTRL1_STOP) == 0) {
break;
}
} while(--loops);
return loops?0:SMBUS_WAIT_UNTIL_READY_TIMEOUT;
}
static int smbus_stop_condition(unsigned smbus_io_base)
{
unsigned char val;
val = inb(smbus_io_base + SMB_CTRL1);
outb(SMB_CTRL1_STOP, smbus_io_base + SMB_CTRL1);
}
static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device)
{
unsigned char val;
@ -86,7 +111,7 @@ static int smbus_send_slave_address(unsigned smbus_io_base, unsigned char device
/* check for bus conflict and NACK */
val = inb(smbus_io_base + SMB_STS);
if ( ((val & SMB_STS_BER) != 0) ||
if (((val & SMB_STS_BER) != 0) ||
((val & SMB_STS_NEGACK) != 0))
return SMBUS_ERROR;
@ -112,7 +137,7 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
/* check for bus conflict and NACK */
val = inb(smbus_io_base + SMB_STS);
if ( ((val & SMB_STS_BER) != 0) ||
if (((val & SMB_STS_BER) != 0) ||
((val & SMB_STS_NEGACK) != 0))
return SMBUS_ERROR;
@ -129,25 +154,27 @@ static int smbus_send_command(unsigned smbus_io_base, unsigned char command)
static unsigned char do_smbus_read_byte(unsigned smbus_io_base, unsigned char device, unsigned char address)
{
unsigned char val;
unsigned char val, val1;
if (smbus_start_condition(smbus_io_base) < 0)
print_debug("smbus error 1");
smbus_check_stop_condition(smbus_io_base);
if (smbus_send_slave_address(smbus_io_base, device) < 0)
print_debug("smbus error 2");
smbus_start_condition(smbus_io_base);
if (smbus_send_command(smbus_io_base, address) < 0)
print_debug("smbus error 3");
smbus_send_slave_address(smbus_io_base, device);
if (smbus_start_condition(smbus_io_base) < 0)
print_debug("smbus error 4");
smbus_send_command(smbus_io_base, address);
if (smbus_send_slave_address(smbus_io_base, device | 0x01))
print_debug("smbus error 5");
smbus_start_condition(smbus_io_base);
smbus_send_slave_address(smbus_io_base, device | 0x01);
/* send NACK to slave */
val = inb(smbus_io_base + SMB_CTRL1);
outb(val | SMB_CTRL1_ACK, smbus_io_base + SMB_CTRL1);
return inb(smbus_io_base + SMB_SDA);
val = inb(smbus_io_base + SMB_SDA);
//smbus_stop_condition(smbus_io_base);
return val;
}