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superio/nct5104d: Refactor IRQ trigger config 

That function was getting too long.

Change-Id: Ic50f210391c2467b65215aa556269b0ba601c2ec
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: http://review.coreboot.org/10176
Tested-by: build bot (Jenkins)
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Reviewed-by: Dave Frodin <dave.frodin@se-eng.com>
This commit is contained in:
Kyösti Mälkki 2015-05-11 20:21:06 +03:00
parent cbcf28fef0
commit 0430c69918
1 changed files with 27 additions and 11 deletions
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38
src/superio/nuvoton/nct5104d/superio.c
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@ -25,16 +25,10 @@
#include "nct5104d.h" #include "nct5104d.h"
#include "chip.h" #include "chip.h"
static void nct5104d_init(struct device *dev) static void set_irq_trigger_type(struct device *dev, bool trig_level)
{ {
struct superio_nuvoton_nct5104d_config *conf = dev->chip_info;
u8 reg10, reg11, reg26; u8 reg10, reg11, reg26;
if (!dev->enabled)
return;
pnp_enter_conf_mode(dev);
//Before accessing CR10 OR CR11 Bit 4 in CR26 must be set to 1 //Before accessing CR10 OR CR11 Bit 4 in CR26 must be set to 1
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26); reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 |= CR26_LOCK_REG; reg26 |= CR26_LOCK_REG;
@ -44,7 +38,7 @@ static void nct5104d_init(struct device *dev)
//SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5 //SP1 (UARTA) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 5
case NCT5104D_SP1: case NCT5104D_SP1:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10); reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (conf->irq_trigger_type) if (trig_level)
reg10 |= (1 << 5); reg10 |= (1 << 5);
else else
reg10 &= ~(1 << 5); reg10 &= ~(1 << 5);
@ -53,7 +47,7 @@ static void nct5104d_init(struct device *dev)
//SP2 (UARTB) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 4 //SP2 (UARTB) IRQ type selection (1:level,0:edge) is controlled by CR 10, bit 4
case NCT5104D_SP2: case NCT5104D_SP2:
reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10); reg10 = pnp_read_config(dev, IRQ_TYPE_SEL_CR10);
if (conf->irq_trigger_type) if (trig_level)
reg10 |= (1 << 4); reg10 |= (1 << 4);
else else
reg10 &= ~(1 << 4); reg10 &= ~(1 << 4);
@ -62,7 +56,7 @@ static void nct5104d_init(struct device *dev)
//SP3 (UARTC) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 5 //SP3 (UARTC) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 5
case NCT5104D_SP3: case NCT5104D_SP3:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11); reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (conf->irq_trigger_type) if (trig_level)
reg11 |= (1 << 5); reg11 |= (1 << 5);
else else
reg11 &= ~(1 << 5); reg11 &= ~(1 << 5);
@ -71,7 +65,7 @@ static void nct5104d_init(struct device *dev)
//SP4 (UARTD) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 4 //SP4 (UARTD) IRQ type selection (1:level,0:edge) is controlled by CR 11, bit 4
case NCT5104D_SP4: case NCT5104D_SP4:
reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11); reg11 = pnp_read_config(dev,IRQ_TYPE_SEL_CR11);
if (conf->irq_trigger_type) if (trig_level)
reg11 |= (1 << 4); reg11 |= (1 << 4);
else else
reg11 &= ~(1 << 4); reg11 &= ~(1 << 4);
@ -85,6 +79,28 @@ static void nct5104d_init(struct device *dev)
reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26); reg26 = pnp_read_config(dev, GLOBAL_OPTION_CR26);
reg26 &= ~CR26_LOCK_REG; reg26 &= ~CR26_LOCK_REG;
pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26); pnp_write_config(dev, GLOBAL_OPTION_CR26, reg26);
}
static void nct5104d_init(struct device *dev)
{
struct superio_nuvoton_nct5104d_config *conf = dev->chip_info;
if (!dev->enabled)
return;
pnp_enter_conf_mode(dev);
switch(dev->path.pnp.device) {
case NCT5104D_SP1:
case NCT5104D_SP2:
case NCT5104D_SP3:
case NCT5104D_SP4:
set_irq_trigger_type(dev, conf->irq_trigger_type != 0);
break;
default:
break;
}
pnp_exit_conf_mode(dev); pnp_exit_conf_mode(dev);
} }