Wield battle axe at ARM port

This patch unfortunately incorporates a number of changes,
all of which are making future ARM ports easier.

 - drop cruft that came in with u-boot
 - move serial console from mainboard Kconfig to Exynos Kconfig
 - factor out non-board specific wakeup code
 - move generic bootblock code from mainboard to Exynos
 - actually call arch_cpu_init()
 - remove dead code
 - fix up copyright messages
 - remove snow_ prefix from a lot of code to reduce the noise
   when creating a new mainboard based on that code.

Change-Id: Ic05326edf5a7e1a691c5ff841a604cb9e351b562
Signed-off-by: Stefan Reinauer <reinauer@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3640
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/arch/armv7/include/common.h

@@ -285,9 +285,6 @@ int	checkicache   (void);
 int	checkdcache   (void);
 void	upmconfig     (unsigned int, unsigned int *, unsigned int);
 unsigned long	get_tbclk     (void);
-#if defined (CONFIG_OF_LIBFDT) && defined (CONFIG_OF_BOARD_SETUP)
-void ft_cpu_setup(void *blob, bd_t *bd);
-#endif
 
 
 /* $(CPU)/serial.c */
@@ -412,9 +409,6 @@ int strcmp_compar(const void *, const void *);
 /* lib/time.c */
 void	udelay        (unsigned long);
 
-/* lib/strmhz.c */
-char *	strmhz(char *buf, unsigned long hz);
-
 /* Multicore arch functions */
 #ifdef CONFIG_MP
 int cpu_status(int nr);
@@ -427,13 +421,6 @@ int cpu_release(int nr, int argc, char * const argv[]);
 
 /* Put only stuff here that the assembler can digest */
 
-#ifdef CONFIG_POST
-#define CONFIG_HAS_POST
-#ifndef CONFIG_POST_ALT_LIST
-#define CONFIG_POST_STD_LIST
-#endif
-#endif
-
 #define ROUND(a,b)		(((a) + (b) - 1) & ~((b) - 1))
 #define DIV_ROUND(n,d)		(((n) + ((d)/2)) / (d))
 #define DIV_ROUND_UP(n,d)	(((n) + (d) - 1) / (d))

src/cpu/samsung/exynos5-common/cpu.h

@@ -61,23 +61,6 @@
 
 
 #include <arch/io.h>
-/* CPU detection macros */
-extern unsigned int s5p_cpu_id;
-
-inline void s5p_set_cpu_id(void);
-
-#define IS_SAMSUNG_TYPE(type, id)			\
-static inline int cpu_is_##type(void)			\
-{							\
-	return s5p_cpu_id == id ? 1 : 0;		\
-}
-
-IS_SAMSUNG_TYPE(s5pc100, 0xc100)
-IS_SAMSUNG_TYPE(s5pc110, 0xc110)
-
-int s5p_get_cpu_rev(void);
-//void s5p_set_cpu_id(void);
-int s5p_get_cpu_id(void);
 
 #define DEVICE_NOT_AVAILABLE		0
 
@@ -132,9 +115,6 @@ enum boot_mode exynos_get_boot_device(void);
  */
 int board_wakeup_permitted(void);
 
-#define cpu_is_exynos4()	(s5p_get_cpu_id() == 0xc210)
-#define cpu_is_exynos5()	(s5p_get_cpu_id() == 0xc520)
-
 /**
  * Init subsystems according to the reset status
  *
@@ -142,4 +122,7 @@ int board_wakeup_permitted(void);
  */
 int lowlevel_init_subsystems(void);
 
+int arch_cpu_init(void);
+
+
 #endif	/* _EXYNOS_COMMON_CPU_H */

src/cpu/samsung/exynos5-common/cpu_info.c

@@ -20,13 +20,9 @@
  * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  * MA 02111-1307 USA
  */
+
+#include <console/console.h>
 #include <common.h>
-#if 0
-#include <asm/io.h>
-#include <asm/arch/clk.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/dmc.h>
-#endif
 #include <arch/io.h>
 
 #include <cpu/samsung/exynos5-common/clk.h>
@@ -39,31 +35,10 @@
 /* FIXME(dhendrix): consolidate samsung ID code/#defines to a common location */
 #include <cpu/samsung/exynos5250/setup.h>	/* cpu_info_init() prototype */
 
-/*
+static unsigned int s5p_cpu_id;
- * The following CPU infos are initialized in lowlevel_init(). They should be
+static unsigned int s5p_cpu_rev;
- * put in the .data section. Otherwise, a compile will put them in the .bss
- * section since they don't have initial values. The relocation code which
- * runs after lowlevel_init() will reset them to zero.
- */
-unsigned int s5p_cpu_id __attribute__((section(".data")));
-unsigned int s5p_cpu_rev __attribute__((section(".data")));
 
-void cpu_info_init(void)
+static void s5p_set_cpu_id(void)
-{
-	s5p_set_cpu_id();
-}
-
-int s5p_get_cpu_id(void)
-{
-	return s5p_cpu_id;
-}
-
-int s5p_get_cpu_rev(void)
-{
-	return s5p_cpu_rev;
-}
-
-void s5p_set_cpu_id(void)
 {
 	s5p_cpu_id = readl((void *)EXYNOS_PRO_ID);
 	s5p_cpu_id = (0xC000 | ((s5p_cpu_id & 0x00FFF000) >> 12));
@@ -80,49 +55,12 @@ void s5p_set_cpu_id(void)
 	}
 }
 
-#ifdef CONFIG_DISPLAY_CPUINFO
-int print_cpuinfo(void)
-{
-	char buf[32];
-
-	printf("CPU:   S5P%X @ %sMHz\n",
-			s5p_cpu_id, strmhz(buf, get_arm_clk()));
-
-	return 0;
-}
-#endif
-
-#if 0
-void board_show_dram(ulong size)
-{
-	enum ddr_mode mem_type;
-	unsigned frequency_mhz;
-	unsigned arm_freq;
-	enum mem_manuf mem_manuf;
-	char buf[32];
-	int ret;
-
-	/* Get settings from the fdt */
-	ret = clock_get_mem_selection(&mem_type, &frequency_mhz,
-				       &arm_freq, &mem_manuf);
-	if (ret)
-		panic("Invalid DRAM information");
-
-	puts("DRAM:  ");
-	print_size(size, " ");
-	printf("%s %s @ %sMHz",
-	       clock_get_mem_manuf_name(mem_manuf),
-	       clock_get_mem_type_name(mem_type),
-	       strmhz(buf, frequency_mhz));
-	putc('\n');
-}
-#endif
-
-#ifdef CONFIG_ARCH_CPU_INIT
 int arch_cpu_init(void)
 {
-	cpu_info_init();
+	s5p_set_cpu_id();
+
+	printk(BIOS_INFO, "CPU:   S5P%X @ %ldMHz\n",
+			s5p_cpu_id, get_arm_clk() / (1024*1024));
 
 	return 0;
 }
-#endif

src/cpu/samsung/exynos5-common/exynos5-common.h

@@ -22,175 +22,24 @@
  * MA 02111-1307 USA
  */
 
-/* TODO(dhendrix): some #defines are commented out here and moved to Kconfig */
-
 #ifndef __EXYNOS5_CONFIG_H
 #define __EXYNOS5_CONFIG_H
 
-/* High Level Configuration Options */
-#define CONFIG_SAMSUNG			/* in a SAMSUNG core */
-#define CONFIG_S5P			/* S5P Family */
-#define CONFIG_EXYNOS5			/* which is in a Exynos5 Family */
-#define BUILD_PART_FS_STUFF	1	/* Disk Partition Support */
-
-#define CONFIG_ARCH_CPU_INIT		/* Used to check cpu type */
-
 #include <cpu/samsung/exynos5250/cpu.h>		/* get chip and board defs */
 
-/* Align LCD to 1MB boundary */
+/* TODO(dhendrix): some #defines are commented out here and moved to Kconfig */
-#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE
-
-#define CONFIG_DISPLAY_CPUINFO
-#define CONFIG_DISPLAY_BOARDINFO_LATE
-#define CONFIG_SYS_CONSOLE_INFO_QUIET
-#define CONFIG_BOARD_LATE_INIT
-
-#define CONFIG_CMD_SHA256
-//#define CONFIG_EXYNOS_ACE_SHA
 
 //#define CONFIG_SYS_SDRAM_BASE		0x40000000
 //#define CONFIG_SYS_TEXT_BASE		0x43e00000
 
-#define CONFIG_SETUP_MEMORY_TAGS
-#define CONFIG_CMDLINE_TAG
-#define CONFIG_INITRD_TAG
-#define CONFIG_CMDLINE_EDITING
-
 /* Power Down Modes */
 #define S5P_CHECK_SLEEP			0x00000BAD
 #define S5P_CHECK_DIDLE			0xBAD00000
 #define S5P_CHECK_LPA			0xABAD0000
 
-/* Offset for inform registers */
-#define INFORM0_OFFSET			0x800
-#define INFORM1_OFFSET			0x804
-
-/* Size of malloc() pool */
-#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))
-
-/* select serial console configuration */
-#define CONFIG_SERIAL_MULTI
-//#define CONFIG_BAUDRATE			115200
-#define EXYNOS5_DEFAULT_UART_OFFSET	0x010000
-
-#define CONFIG_BOARD_EARLY_INIT_F
-
-/* PWM */
-#define CONFIG_PWM
-
-/* allow to overwrite serial and ethaddr */
-#define CONFIG_ENV_OVERWRITE
-
-/* SPL */
-#define CONFIG_SPL
-#define CONFIG_SPL_GPIO_SUPPORT
-#define CONFIG_SPL_POWER_SUPPORT
-#define CONFIG_SPL_I2C_SUPPORT
-#define CONFIG_SPL_SERIAL_SUPPORT
-#define CONFIG_SPL_LIBCOMMON_SUPPORT
-
-/* Number of GPIOS to use for board revision detection */
-#define CONFIG_BOARD_REV_GPIO_COUNT	2
-
-/* Miscellaneous configurable options */
-#define CONFIG_SYS_LONGHELP		/* undef to save memory */
-#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser	*/
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
-#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
-#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
-/* Boot Argument Buffer Size */
-#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
-/* memtest works on */
-#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
-#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5E00000)
-#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x3E00000)
-
 #define CONFIG_SYS_HZ			1000
 
-/* valid baudrates */
-#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }
-
-/* Stack sizes */
-#define CONFIG_STACKSIZE		(256 << 10)	/* 256KB */
-
-#define CONFIG_SYS_MONITOR_BASE	0x00000000
-
-#ifdef CONFIG_SPI_FLASH
-/* Enable SPI H/W Controller Driver support */
-#define CONFIG_EXYNOS_SPI
-
-/* FIXME(dhendrix): We should be concerned with SPI flash parts here... */
-#if 0
-#define CONFIG_CMD_SF
-#define CONFIG_CMD_SPI
-#define CONFIG_SPI_FLASH_WINBOND
-/* Enable Gigadevice SPI flash support for Snow board */
-#define CONFIG_SPI_FLASH_GIGADEVICE
-#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0
-/* Set speed for SPI flash */
-#define CONFIG_SF_DEFAULT_SPEED	50000000
-#endif
-#endif
-
-/* FLASH and environment organization */
-#define CONFIG_SYS_NO_FLASH
-#undef CONFIG_CMD_IMLS
-
-#define CONFIG_SECURE_BL1_ONLY
-
-/* Secure FW size configuration */
-#ifdef CONFIG_SECURE_BL1_ONLY
-#define CONFIG_SEC_FW_SIZE		(8 << 10)	/* 8KB */
-#else
-#define CONFIG_SEC_FW_SIZE		0
-#endif
-
-/* Configuration of BL1, BL2, ENV Blocks on mmc */
-#define CONFIG_RES_BLOCK_SIZE	(512)
-#define CONFIG_BL1_SIZE		(16 << 10) /*16 K reserved for BL1*/
-#define CONFIG_BL2_SIZE		(512UL << 10UL)	/* 512 KB */
-#define CONFIG_ENV_SIZE		(16 << 10)	/* 16 KB */
-
-#define CONFIG_BL1_OFFSET	(CONFIG_RES_BLOCK_SIZE + CONFIG_SEC_FW_SIZE)
-#define CONFIG_BL2_OFFSET	(CONFIG_BL1_OFFSET + CONFIG_BL1_SIZE)
-
-#define SPI_FLASH_UBOOT_POS	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE)
-
-#ifdef CONFIG_ENV_IS_IN_SPI_FLASH
-#define CONFIG_ENV_SPI_MODE	SPI_MODE_0
-#define CONFIG_ENV_OFFSET	(CONFIG_SEC_FW_SIZE + CONFIG_BL1_SIZE + \
-				 CONFIG_BL2_SIZE)
-#define CONFIG_ENV_SECT_SIZE	CONFIG_ENV_SIZE
-#define CONFIG_ENV_SPI_BUS	1
-#else /* CONFIG_ENV_IS_IN_MMC */
-#define CONFIG_ENV_OFFSET	(CONFIG_BL2_OFFSET + CONFIG_BL2_SIZE)
-#endif
-
-/* U-boot copy size from boot Media to DRAM.*/
-#define BL2_START_OFFSET	(CONFIG_BL2_OFFSET/512)
-
-/* Set the emmc bus width to 8 */
-#define CONFIG_MSHCI_BUS_WIDTH	8
-#define CONFIG_MSHCI_PERIPH_ID	PERIPH_ID_SDMMC0
-
-#if BUILD_PART_FS_STUFF
-#define CONFIG_DOS_PARTITION
-#define CONFIG_EFI_PARTITION
-#endif
-
-/* Enable devicetree support */
-#define CONFIG_OF_LIBFDT
-
-#define CONFIG_SYS_THUMB_BUILD
-
 /* We spend about 100us getting from reset to SPL */
 #define CONFIG_SPL_TIME_US	100000
 
-/* Stringify a token */
-#ifndef STRINGIFY
-#define _STRINGIFY(x)	#x
-#define STRINGIFY(x)	_STRINGIFY(x)
-#endif
-
 #endif	/* __EXYNOS5_CONFIG_H */

src/cpu/samsung/exynos5250/Kconfig

@@ -97,3 +97,41 @@ config SYS_TEXT_BASE
 config COREBOOT_TABLES_SIZE
 	hex
 	default 0x4000000
+
+choice CONSOLE_SERIAL_UART_CHOICES
+	prompt "Serial Console UART"
+	default CONSOLE_SERIAL_UART3
+	depends on CONSOLE_SERIAL_UART
+
+config CONSOLE_SERIAL_UART0
+	bool "UART0"
+	help
+	  Serial console on UART0
+
+config CONSOLE_SERIAL_UART1
+	bool "UART1"
+	help
+	  Serial console on UART1
+
+config CONSOLE_SERIAL_UART2
+	bool "UART2"
+	help
+	  Serial console on UART2
+
+config CONSOLE_SERIAL_UART3
+	bool "UART3"
+	help
+	  Serial console on UART3
+
+endchoice
+
+config CONSOLE_SERIAL_UART_ADDRESS
+	hex
+	depends on CONSOLE_SERIAL_UART
+	default 0x12c00000 if CONSOLE_SERIAL_UART0
+	default 0x12c10000 if CONSOLE_SERIAL_UART1
+	default 0x12c20000 if CONSOLE_SERIAL_UART2
+	default 0x12c30000 if CONSOLE_SERIAL_UART3
+	help
+	  Map the UART names to the respective MMIO address.
+

src/cpu/samsung/exynos5250/Makefile.inc

@@ -10,6 +10,7 @@ bootblock-$(CONFIG_EARLY_CONSOLE) += clock.c
 bootblock-$(CONFIG_EARLY_CONSOLE) += monotonic_timer.c
 bootblock-$(CONFIG_EARLY_CONSOLE) += soc.c
 bootblock-$(CONFIG_EARLY_CONSOLE) += uart.c
+bootblock-y += wakeup.c
 
 romstage-y += clock.c
 romstage-y += clock_init.c
@@ -21,6 +22,7 @@ romstage-y += mct.c
 romstage-y += monotonic_timer.c
 romstage-$(CONFIG_EARLY_CONSOLE) += soc.c
 romstage-$(CONFIG_EARLY_CONSOLE) += uart.c
+romstage-y += wakeup.c
 
 #ramstage-y += tzpc_init.c
 ramstage-y += clock.c

src/cpu/samsung/exynos5250/bootblock.c

@@ -17,7 +17,27 @@
  * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
  */
 
+#include <console/console.h>
+#include "clk.h"
+#include "wakeup.h"
+
 void bootblock_cpu_init(void);
 void bootblock_cpu_init(void)
 {
+	/* kick off the multi-core timer.
+	 * We want to do this as early as we can.
+	 */
+	mct_start();
+
+	if (get_wakeup_state() == WAKEUP_DIRECT) {
+		wakeup();
+		/* Never returns. */
+	}
+
+	/* For most ARM systems, we have to initialize firmware media source
+	 * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
+	 * already handled by iROM so there's no need to setup again.
+	 */
+
+	console_init();
 }

src/cpu/samsung/exynos5250/cpu.c

@@ -8,6 +8,7 @@
 #include <arch/cache.h>
 #include <cpu/samsung/exynos5250/fimd.h>
 #include <cpu/samsung/exynos5-common/s5p-dp-core.h>
+#include <cpu/samsung/exynos5-common/cpu.h>
 #include "chip.h"
 #include "cpu.h"
 
@@ -97,6 +98,8 @@ static void cpu_init(device_t dev)
 {
 	exynos_displayport_init(dev);
 	ram_resource(dev, 0, RAM_BASE_KB, RAM_SIZE_KB);
+
+	arch_cpu_init();
 }
 
 static void cpu_noop(device_t dev)

src/cpu/samsung/exynos5250/wakeup.c

@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.  All rights reserved.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#include <console/console.h>
+#include <cpu/samsung/exynos5250/power.h>
+#include <cpu/samsung/exynos5-common/exynos5-common.h>
+
+#include "wakeup.h"
+
+void wakeup(void)
+{
+	if (wakeup_need_reset())
+		power_reset();
+
+	power_init();  /* Ensure ps_hold_setup() for early wakeup. */
+	power_exit_wakeup();
+	/* Should never return. */
+	die("Failed to wake up.\n");
+}
+
+int get_wakeup_state(void)
+{
+	uint32_t status = power_read_reset_status();
+
+	/* DIDLE/LPA can be resumed without clock reset (ex, bootblock),
+	 * and SLEEP requires resetting clock (should be done in ROM stage).
+	 */
+
+	if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA)
+		return WAKEUP_DIRECT;
+
+	if (status == S5P_CHECK_SLEEP)
+		return WAKEUP_NEED_CLOCK_RESET;
+
+	return IS_NOT_WAKEUP;
+}

src/cpu/samsung/exynos5250/wakeup.h

@@ -0,0 +1,37 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef WAKEUP_H
+#define WAKEUP_H
+
+enum {
+	// A normal boot (not suspend/resume)
+	IS_NOT_WAKEUP,
+	// A wake up event that can be resumed any time
+	WAKEUP_DIRECT,
+	// A wake up event that must be resumed only after
+	// clock and memory controllers are re-initialized
+	WAKEUP_NEED_CLOCK_RESET,
+};
+
+int wakeup_need_reset(void);
+int get_wakeup_state(void);
+void wakeup(void);
+
+#endif	/* WAKEUP_H */

src/mainboard/google/snow/Kconfig

@@ -28,7 +28,6 @@ config BOARD_SPECIFIC_OPTIONS # dummy
 	select EC_GOOGLE_CHROMEEC_I2C
 	select BOARD_ROMSIZE_KB_4096
 	select DRIVER_MAXIM_MAX77686
-#	select HAVE_ACPI_TABLES
 	select EXYNOS_DISPLAYPORT
 	select CHROMEOS
 	select DRIVER_TI_TPS65090
@@ -41,132 +40,18 @@ config MAINBOARD_DIR
 
 config MAINBOARD_PART_NUMBER
 	string
-	default "SNOW"
+	default "Snow"
-
-#config MMCONF_BASE_ADDRESS
-#	hex
-#	default 0xf0000000
-
-#config IRQ_SLOT_COUNT
-#	int
-#	default 18
 
 config MAX_CPUS
 	int
 	default 2
 
-config MAINBOARD_VENDOR
-	string
-	default "Samsung"
-
-config BOOTBLOCK_MAINBOARD_INIT
-	string
-	default "mainboard/google/snow/bootblock.c"
-
 config DRAM_SIZE_MB
 	int
 	default 2048
 
-config NR_DRAM_BANKS
-	int
-	default 1
-
-choice CONSOLE_SERIAL_UART_CHOICES
-	prompt "Serial Console UART"
-	default CONSOLE_SERIAL_UART3
-	depends on CONSOLE_SERIAL_UART
-
-config CONSOLE_SERIAL_UART0
-	bool "UART0"
-	help
-	  Serial console on UART0
-
-config CONSOLE_SERIAL_UART1
-	bool "UART1"
-	help
-	  Serial console on UART1
-
-config CONSOLE_SERIAL_UART2
-	bool "UART2"
-	help
-	  Serial console on UART2
-
-config CONSOLE_SERIAL_UART3
-	bool "UART3"
-	help
-	  Serial console on UART3
-
-endchoice
-
-config CONSOLE_SERIAL_UART_ADDRESS
-	hex
-	depends on CONSOLE_SERIAL_UART
-	default 0x12c00000 if CONSOLE_SERIAL_UART0
-	default 0x12c10000 if CONSOLE_SERIAL_UART1
-	default 0x12c20000 if CONSOLE_SERIAL_UART2
-	default 0x12c30000 if CONSOLE_SERIAL_UART3
-	help
-	  Map the UART names to the respective MMIO address.
-
 config EC_GOOGLE_CHROMEEC_I2C_BUS
 	hex
 	default 4
 
-#################################################################
-#   stuff from smdk5250.h                                       #
-#   FIXME: can we move some of these to exynos5250's Kconfig?   #
-#################################################################
-config SYS_I2C_SPEED
-	int
-	default 100000
-
-config SYS_I2C_SLAVE
-	hex
-	default 0x0
-
-config I2C_MULTI_BUS
-	bool
-	default y
-
-#config HARD_I2C
-#	bool
-#	default y
-#CMD_I2C
-#I2C_EDID
-#DRIVER_S3C24X0_I2C
-
-config VDD_ARM_MV
-	int
-	default 1300	#1.3V
-
-config VDD_INT_UV
-	int
-	default 1012500	# 1.0125v
-
-config VDD_MIF_MV
-	int
-	default 1000	# 1.0v
-
-config VDD_G3D_MV
-	int
-	default 1200	# 1.2v
-
-config VDD_LDO2_MV
-	int
-	default 1500	# 1.5v
-
-config VDD_LDO3_MV
-	int
-	default 1800	# 1.8v
-
-config VDD_LDO5_MV
-	int
-	default 1800	# 1.8v
-
-config VDD_LDO10_MV
-	int
-	default 1800	# 1.8v
-
-######### smdk5250.h ########
-
 endif # BOARD_GOOGLE_SNOW

src/mainboard/google/snow/Makefile.inc

@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+## Copyright (C) 2012 Google Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -23,6 +23,5 @@ romstage-y += memory.c
 romstage-y += romstage.c
 romstage-y += wakeup.c
 
-# ramstage-y += ec.c
 ramstage-y += mainboard.c
 ramstage-y += chromeos.c

src/mainboard/google/snow/bootblock.c

@@ -1,49 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 The ChromiumOS Authors.  All rights reserved.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- */
-
-#include <types.h>
-#include <arch/io.h>
-#include <cbfs.h>
-#include <uart.h>
-#include <console/console.h>
-#include <cpu/samsung/exynos5250/clk.h>
-#include <cpu/samsung/exynos5250/periph.h>
-#include <cpu/samsung/exynos5250/pinmux.h>
-#include "mainboard.h"
-
-void bootblock_mainboard_init(void);
-void bootblock_mainboard_init(void)
-{
-	/* kick off the multi-core timer.
-	 * We want to do this as early as we can.
-	 */
-	mct_start();
-
-	if (snow_get_wakeup_state() == SNOW_WAKEUP_DIRECT) {
-		snow_wakeup();
-		/* Never returns. */
-	}
-
-	/* For most ARM systems, we have to initialize firmware media source
-	 * (ex, SPI, SD/MMC, or eMMC) now; but for Exynos platform, that is
-	 * already handled by iROM so there's no need to setup again.
-	 */
-
-	console_init();
-}

src/mainboard/google/snow/devicetree.cb

@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2012 The ChromiumOS Authors.  All rights reserved.
+## Copyright (C) 2012 Google Inc.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by

src/mainboard/google/snow/exynos5250.h

@@ -0,0 +1,33 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Google, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+/* I2C */
+#define I2C_0_SPEED 100000
+#define I2C_SLAVE 0
+
+/* Voltages */
+#define VDD_ARM_MV 1300		// 1.3V
+#define VDD_INT_UV 1012500	// 1.0125V
+#define VDD_MIF_MV 1000		// 1.0V
+#define VDD_G3D_MV 1200		// 1.2V
+#define VDD_LDO2_MV 1500	// 1.5V
+#define VDD_LDO3_MV 1800	// 1.8V
+#define VDD_LDO5_MV 1800	// 1.8V
+#define VDD_LDO10_MV 1800	// 1.8V
+

src/mainboard/google/snow/mainboard.c

@@ -1,10 +1,11 @@
 /*
- * Copyright (C) 2012 Google Inc.
+ * This file is part of the coreboot project.
  *
- * This program is free software; you can redistribute it and/or
+ * Copyright (C) 2013 Google, Inc.
- * modify it under the terms of the GNU General Public License as
+ *
- * published by the Free Software Foundation; version 2 of
+ * This program is free software; you can redistribute it and/or modify
- * the License.
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
  *
  * This program is distributed in the hope that it will be useful,
  * but WITHOUT ANY WARRANTY; without even the implied warranty of
@@ -13,8 +14,7 @@
  *
  * You should have received a copy of the GNU General Public License
  * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
- * MA 02111-1307 USA
  */
 
 #include <console/console.h>
@@ -38,13 +38,14 @@
 #include <cpu/samsung/exynos5-common/i2c.h>
 #include <cpu/samsung/exynos5-common/s5p-dp-core.h>
 
+#include "exynos5250.h"
 
 /* convenient shorthand (in MB) */
 #define DRAM_START	(CONFIG_SYS_SDRAM_BASE >> 20)
 #define DRAM_SIZE	CONFIG_DRAM_SIZE_MB
 #define DRAM_END	(DRAM_START + DRAM_SIZE)	/* plus one... */
 
-static struct edid snow_edid = {
+static struct edid edid = {
 	.ha = 1366,
 	.va = 768,
 	.bpp = 16,
@@ -114,14 +115,14 @@ static void exynos_dp_reset(void)
 #define LCD_T5_DELAY_MS	10
 #define LCD_T6_DELAY_MS	10
 
-static void snow_backlight_pwm(void)
+static void backlight_pwm(void)
 {
 	/*Configure backlight PWM as a simple output high (100% brightness) */
 	gpio_direction_output(GPIO_B20, 1);
 	udelay(LCD_T6_DELAY_MS * 1000);
 }
 
-static void snow_backlight_en(void)
+static void backlight_en(void)
 {
 	/* * Configure GPIO for LCD_BL_EN */
 	gpio_direction_output(GPIO_X30, 1);
@@ -132,13 +133,13 @@ static void snow_backlight_en(void)
 #define FET1_CTRL	0x0f
 #define FET6_CTRL	0x14
 
-static void snow_lcd_vdd(void)
+static void lcd_vdd(void)
 {
 	/* Enable FET6, lcd panel */
 	tps65090_fet_enable(TPS69050_BUS, FET6_CTRL);
 }
 
-static void snow_backlight_vdd(void)
+static void backlight_vdd(void)
 {
 	/* Enable FET1, backlight */
 	tps65090_fet_enable(TPS69050_BUS, FET1_CTRL);
@@ -146,7 +147,7 @@ static void snow_backlight_vdd(void)
 }
 
 //static struct video_info smdk5250_dp_config = {
-static struct video_info snow_dp_video_info = {
+static struct video_info dp_video_info = {
 	/* FIXME: fix video_info struct to use const for name */
 	.name			= (char *)"eDP-LVDS NXP PTN3460",
 
@@ -165,7 +166,7 @@ static struct video_info snow_dp_video_info = {
 
 /* FIXME: move some place more appropriate */
 #define EXYNOS5250_DP1_BASE	0x145b0000
-#define SNOW_MAX_DP_TRIES	5
+#define MAX_DP_TRIES	5
 
 /*
  * This function disables the USB3.0 PLL to save power
@@ -183,12 +184,12 @@ static void mainboard_init(device_t dev)
 	int dp_tries;
 	struct s5p_dp_device dp_device = {
 		.base = (struct exynos5_dp *)EXYNOS5250_DP1_BASE,
-		.video_info = &snow_dp_video_info,
+		.video_info = &dp_video_info,
 	};
 	void *fb_addr;
 
-	i2c_init(TPS69050_BUS, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_init(TPS69050_BUS, I2C_0_SPEED, I2C_SLAVE);
-	i2c_init(7, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
+	i2c_init(7, I2C_0_SPEED, I2C_SLAVE);
 
 	tmu_init(&exynos5250_tmu_info);
 
@@ -199,15 +200,15 @@ static void mainboard_init(device_t dev)
 	disable_usb30_pll();
 
 	fb_addr = cbmem_find(CBMEM_ID_CONSOLE);
-	set_vbe_mode_info_valid(&snow_edid, (uintptr_t)(fb_addr) + 64*KiB);
+	set_vbe_mode_info_valid(&edid, (uintptr_t)(fb_addr) + 64*KiB);
 
-	snow_lcd_vdd();
+	lcd_vdd();
 	do {
 		udelay(50);
 	} while (!exynos_dp_hotplug());
 
 	exynos_dp_bridge_setup();
-	for (dp_tries = 1; dp_tries <= SNOW_MAX_DP_TRIES; dp_tries++) {
+	for (dp_tries = 1; dp_tries <= MAX_DP_TRIES; dp_tries++) {
 		exynos_dp_bridge_init();
 		if (exynos_dp_hotplug()) {
 			exynos_dp_reset();
@@ -219,14 +220,14 @@ static void mainboard_init(device_t dev)
 
 		udelay(LCD_T3_DELAY_MS * 1000);
 
-		snow_backlight_vdd();
+		backlight_vdd();
-		snow_backlight_pwm();
+		backlight_pwm();
-		snow_backlight_en();
+		backlight_en();
 		/* if we're here, we're successful */
 		break;
 	}
 
-	if (dp_tries > SNOW_MAX_DP_TRIES)
+	if (dp_tries > MAX_DP_TRIES)
 		printk(BIOS_ERR, "%s: Failed to set up displayport\n", __func__);
 }
 
@@ -235,6 +236,7 @@ static void mainboard_enable(device_t dev)
 	dev->ops->init = &mainboard_init;
 
 	/* set up coreboot tables */
+	/* FIXME: this should happen somewhere else */
 	high_tables_size = CONFIG_COREBOOT_TABLES_SIZE;
 	high_tables_base = CONFIG_SYS_SDRAM_BASE +
 				((unsigned)CONFIG_DRAM_SIZE_MB << 20ULL) -

src/mainboard/google/snow/mainboard.h

@@ -1,33 +0,0 @@
-/*
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
- */
-
-#ifndef MAINBOARD_H
-#define MAINBOARD_H
-enum {
-	SNOW_IS_NOT_WAKEUP,  // A normal boot (not suspend/resume).
-	SNOW_WAKEUP_DIRECT,  // A wake up event that can be resumed any time.
-	SNOW_WAKEUP_NEED_CLOCK_RESET,  // A wake up event that must be resumed
-					// only after clock and memory
-					// controllers are re-initialized.
-};
-
-int snow_get_wakeup_state(void);
-void snow_wakeup(void);
-
-#endif	/* MAINBOARD_H */

src/mainboard/google/snow/memory.c

@@ -1,9 +1,8 @@
 /*
- * This file is part of the coreboot project. It is based off code
+ * This file is part of the coreboot project.
- * from Das U-Boot.
  *
  * Copyright (C) 2012 Samsung Electronics
- * Copyright (C) 2013 The ChromiumOS Authors.
+ * Copyright (C) 2013 Google Inc.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -30,8 +29,6 @@
 #include <cpu/samsung/exynos5250/dmc.h>
 #include <cpu/samsung/exynos5250/clock_init.h>
 
-#include "mainboard.h"
-
 const struct mem_timings mem_timings[] = {
 	{
 		.mem_manuf = MEM_MANUF_ELPIDA,
@@ -453,10 +450,10 @@ const struct mem_timings mem_timings[] = {
 	}
 };
 
-#define SNOW_BOARD_ID0_GPIO	88	/* GPD0, pin 0 */
+#define BOARD_ID0_GPIO	88	/* GPD0, pin 0 */
-#define SNOW_BOARD_ID1_GPIO	89	/* GPD0, pin 1 */
+#define BOARD_ID1_GPIO	89	/* GPD0, pin 1 */
 
-enum snow_board_config {
+enum board_config {
 	SNOW_CONFIG_UNKNOWN = -1,
 	SNOW_CONFIG_SAMSUNG_EVT,
 	SNOW_CONFIG_ELPIDA_EVT,
@@ -471,8 +468,8 @@ enum snow_board_config {
 
 struct {
 	enum mvl3 id0, id1;
-	enum snow_board_config config;
+	enum board_config config;
-} snow_id_map[] = {
+} id_map[] = {
 	/*  ID0      ID1         config */
 	{ LOGIC_0, LOGIC_0, SNOW_CONFIG_SAMSUNG_MP },
 	{ LOGIC_0, LOGIC_1, SNOW_CONFIG_ELPIDA_MP },
@@ -489,17 +486,17 @@ static int board_get_config(void)
 {
 	int i;
 	int id0, id1;
-	enum snow_board_config config = SNOW_CONFIG_UNKNOWN;
+	enum board_config config = SNOW_CONFIG_UNKNOWN;
 
-	id0 = gpio_read_mvl3(SNOW_BOARD_ID0_GPIO);
+	id0 = gpio_read_mvl3(BOARD_ID0_GPIO);
-	id1 = gpio_read_mvl3(SNOW_BOARD_ID1_GPIO);
+	id1 = gpio_read_mvl3(BOARD_ID1_GPIO);
 	if (id0 < 0 || id1 < 0)
 		return -1;
 	printk(BIOS_DEBUG, "%s: id0: %u, id1: %u\n", __func__, id0, id1);
 
-	for (i = 0; i < ARRAY_SIZE(snow_id_map); i++) {
+	for (i = 0; i < ARRAY_SIZE(id_map); i++) {
-		if (id0 == snow_id_map[i].id0 && id1 == snow_id_map[i].id1) {
+		if (id0 == id_map[i].id0 && id1 == id_map[i].id1) {
-			config = snow_id_map[i].config;
+			config = id_map[i].config;
 			break;
 		}
 	}
@@ -507,18 +504,17 @@ static int board_get_config(void)
 	return config;
 }
 
-
 struct mem_timings *get_mem_timings(void)
 {
 	int i;
-	enum snow_board_config board_config;
+	enum board_config config;
 	enum ddr_mode mem_type;
 	unsigned int frequency_mhz;
 	enum mem_manuf mem_manuf;
 	const struct mem_timings *mem;
 	
-	board_config = board_get_config();
+	config = board_get_config();
-	switch (board_config) {
+	switch (config) {
 	case SNOW_CONFIG_ELPIDA_EVT:
 	case SNOW_CONFIG_ELPIDA_DVT:
 	case SNOW_CONFIG_ELPIDA_PVT:
@@ -536,7 +532,7 @@ struct mem_timings *get_mem_timings(void)
 		frequency_mhz = 800;
 		break;
 	default:
-		printk(BIOS_CRIT, "Unable to determine board config\n");
+		printk(BIOS_CRIT, "Unknown board configuration.\n");
 		return NULL;
 	}
 

src/mainboard/google/snow/romstage.c

@@ -34,25 +34,26 @@
 #include <cpu/samsung/exynos5250/periph.h>
 #include <cpu/samsung/exynos5250/power.h>
 #include <cpu/samsung/exynos5250/clock_init.h>
+#include <cpu/samsung/exynos5250/wakeup.h>
 #include <console/console.h>
 #include <arch/stages.h>
 
 #include <drivers/maxim/max77686/max77686.h>
 #include <device/i2c.h>
 
-#include "mainboard.h"
+#include "exynos5250.h"
 
 #define PMIC_BUS	0
 #define MMC0_GPIO_PIN	(58)
 
-static void snow_setup_power(void)
+static void setup_power(void)
 {
 	int error = 0;
 
 	power_init();
 
 	/* Initialize I2C bus to configure PMIC. */
-	i2c_init(0, CONFIG_SYS_I2C_SPEED, 0x00);
+	i2c_init(0, I2C_0_SPEED, 0x00);
 
 	printk(BIOS_DEBUG, "%s: Setting up PMIC...\n", __func__);
 	/*
@@ -67,21 +68,21 @@ static void snow_setup_power(void)
 	 */
 	error = max77686_disable_backup_batt(PMIC_BUS);
 
-	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, CONFIG_VDD_ARM_MV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK2, VDD_ARM_MV,
 						REG_ENABLE, MAX77686_MV);
-	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, CONFIG_VDD_INT_UV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK3, VDD_INT_UV,
 						REG_ENABLE, MAX77686_UV);
-	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, CONFIG_VDD_MIF_MV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK1, VDD_MIF_MV,
 						REG_ENABLE, MAX77686_MV);
-	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, CONFIG_VDD_G3D_MV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_BUCK4, VDD_G3D_MV,
 						REG_ENABLE, MAX77686_MV);
-	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, CONFIG_VDD_LDO2_MV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO2, VDD_LDO2_MV,
 						REG_ENABLE, MAX77686_MV);
-	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, CONFIG_VDD_LDO3_MV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO3, VDD_LDO3_MV,
 						REG_ENABLE, MAX77686_MV);
-	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, CONFIG_VDD_LDO5_MV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO5, VDD_LDO5_MV,
 						REG_ENABLE, MAX77686_MV);
-	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, CONFIG_VDD_LDO10_MV,
+	error |= max77686_volsetting(PMIC_BUS, PMIC_LDO10, VDD_LDO10_MV,
 						REG_ENABLE, MAX77686_MV);
 
 	error |= max77686_enable_32khz_cp(PMIC_BUS);
@@ -92,7 +93,7 @@ static void snow_setup_power(void)
 	}
 }
 
-static void snow_setup_storage(void)
+static void setup_storage(void)
 {
 	/* MMC0: Fixed, 8 bit mode, connected with GPIO. */
 	if (clock_set_mshci(PERIPH_ID_SDMMC0))
@@ -109,12 +110,12 @@ static void snow_setup_storage(void)
 	exynos_pinmux_config(PERIPH_ID_SDMMC2, 0);
 }
 
-static void snow_setup_graphics(void)
+static void setup_graphics(void)
 {
 	exynos_pinmux_config(PERIPH_ID_DPHPD, 0);
 }
 
-static void snow_setup_gpio(void)
+static void setup_gpio(void)
 {
 	struct exynos5_gpio_part1 *gpio_pt1;
 	struct exynos5_gpio_part2 *gpio_pt2;
@@ -142,7 +143,7 @@ static void snow_setup_gpio(void)
 	s5p_gpio_set_pull(&gpio_pt2->x1, POWER_GPIO, EXYNOS_GPIO_PULL_NONE);
 }
 
-static void snow_setup_memory(struct mem_timings *mem, int is_resume)
+static void setup_memory(struct mem_timings *mem, int is_resume)
 {
 	printk(BIOS_SPEW, "man: 0x%x type: 0x%x, div: 0x%x, mhz: 0x%x\n",
 	       mem->mem_manuf,
@@ -162,7 +163,7 @@ static void snow_setup_memory(struct mem_timings *mem, int is_resume)
 	}
 }
 
-static struct mem_timings *snow_setup_clock(void)
+static struct mem_timings *setup_clock(void)
 {
 	struct mem_timings *mem = get_mem_timings();
 	struct arm_clk_ratios *arm_ratios = get_arm_clk_ratios();
@@ -177,31 +178,30 @@ void main(void)
 {
 	struct mem_timings *mem;
 	void *entry;
-	int is_resume = (snow_get_wakeup_state() != SNOW_IS_NOT_WAKEUP);
+	int is_resume = (get_wakeup_state() != IS_NOT_WAKEUP);
 
 	/* Clock must be initialized before console_init, otherwise you may need
 	 * to re-initialize serial console drivers again. */
-	mem = snow_setup_clock();
+	mem = setup_clock();
 
 	if (!is_resume) {
 		console_init();
-		snow_setup_power();
+		setup_power();
 	}
 
-	snow_setup_memory(mem, is_resume);
+	setup_memory(mem, is_resume);
 
 	if (is_resume) {
-		snow_wakeup();
+		wakeup();
 	}
 
-	snow_setup_storage();
+	setup_storage();
-	snow_setup_gpio();
+	setup_gpio();
-	snow_setup_graphics();
+	setup_graphics();
 
 	/* Set SPI (primary CBFS media) clock to 50MHz. */
 	clock_set_rate(PERIPH_ID_SPI1, 50000000);
-	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
-	printk(BIOS_INFO, "entry is 0x%p, leaving romstage.\n", entry);
 
+	entry = cbfs_load_stage(CBFS_DEFAULT_MEDIA, "fallback/coreboot_ram");
 	stage_exit(entry);
 }

src/mainboard/google/snow/wakeup.c

@@ -24,39 +24,12 @@
 #include <cpu/samsung/exynos5250/power.h>
 #include <cpu/samsung/exynos5-common/exynos5-common.h>
 
-#include "mainboard.h"
+#include <cpu/samsung/exynos5250/wakeup.h>
 
-static int snow_wakeup_need_reset(void)
+int wakeup_need_reset(void)
 {
 	/* The "wake up" event is not reliable (known as "bad wakeup") and needs
 	 * reset if GPIO value is high. */
 	return gpio_get_value(GPIO_Y10);
 }
 
-void snow_wakeup(void)
-{
-	if (snow_wakeup_need_reset())
-		power_reset();
-
-	power_init();  /* Ensure ps_hold_setup() for early wakeup. */
-	power_exit_wakeup();
-	/* Should never return. */
-	die("Failed to wake up.\n");
-}
-
-int snow_get_wakeup_state()
-{
-	uint32_t status = power_read_reset_status();
-
-	/* DIDLE/LPA can be resumed without clock reset (ex, bootblock),
-	 * and SLEEP requires resetting clock (should be done in ROM stage).
-	 */
-
-	if (status == S5P_CHECK_DIDLE || status == S5P_CHECK_LPA)
-		return SNOW_WAKEUP_DIRECT;
-
-	if (status == S5P_CHECK_SLEEP)
-		return SNOW_WAKEUP_NEED_CLOCK_RESET;
-
-	return SNOW_IS_NOT_WAKEUP;
-}