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tegra124: Use correct mask for APB bus width 

It worked earlier since the APB and AHB bus widths occupy the same bits
in their respective registers.

BUG=none
BRANCH=none
TEST=tested on Nyan
Signed-off-by: David Hendricks <dhendrix@chromium.org>

Original-Change-Id: I9b18c648c60dcc4ad62ca1f514d253f8cccaeee7
Original-Reviewed-on: https://chromium-review.googlesource.com/194478
Original-Tested-by: David Hendricks <dhendrix@chromium.org>
Original-Reviewed-by: Gabe Black <gabeblack@chromium.org>
Original-Commit-Queue: David Hendricks <dhendrix@chromium.org>
(cherry picked from commit 1d912302e9dcc9c6ba69e15434bb1841e1196208)
Signed-off-by: Marc Jones <marc.jones@se-eng.com>

Change-Id: I2ea7ac83d3501876df52018aed467ec33074817e
Reviewed-on: http://review.coreboot.org/7760
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
This commit is contained in:
David Hendricks 2014-04-09 16:02:52 -07:00 committed by Marc Jones
parent c05a90595d
commit 0446563747
1 changed files with 1 additions and 1 deletions
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2
src/soc/nvidia/tegra124/spi.c
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@ -453,7 +453,7 @@ static void setup_dma_params(struct tegra_spi_channel *spi,
{ {
/* APB bus width = 8-bits, address wrap for each word */ /* APB bus width = 8-bits, address wrap for each word */
clrbits_le32(&dma->regs->apb_seq, clrbits_le32(&dma->regs->apb_seq,
AHB_BUS_WIDTH_MASK << AHB_BUS_WIDTH_SHIFT); APB_BUS_WIDTH_MASK << APB_BUS_WIDTH_SHIFT);
/* AHB 1 word burst, bus width = 32 bits (fixed in hardware), /* AHB 1 word burst, bus width = 32 bits (fixed in hardware),
* no address wrapping */ * no address wrapping */
clrsetbits_le32(&dma->regs->ahb_seq, clrsetbits_le32(&dma->regs->ahb_seq,