Add support for the Intel 82371FB PIIX and 82371SB (PIIX3) southbridges.
Tested on PIIX3 hardware. Signed-off-by: Uwe Hermann <uwe@hermann-uwe.de> Acked-by: Corey Osgood <corey.osgood@gmail.com> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@3694 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -125,6 +125,7 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
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/* Set bit 9: 1-Meg Extended BIOS Enable (PCI master accesses to
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* FFF00000-FFF7FFFF are forwarded to ISA).
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* Note: This bit is reserved on PIIX/PIIX3.
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* Set bit 7: Extended BIOS Enable (PCI master accesses to
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* FFF80000-FFFDFFFF are forwarded to ISA).
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* Set bit 6: Lower BIOS Enable (PCI master, or ISA master accesses to
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@ -134,7 +135,10 @@ static int enable_flash_piix4(struct pci_dev *dev, const char *name)
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* Note: Accesses to FFFF0000-FFFFFFFF are always forwarded to ISA.
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* Set bit 2: BIOSCS# Write Enable (1=enable, 0=disable).
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*/
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new = old | 0x02c4;
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if (dev->device_id == 0x122e || dev->device_id == 0x7000)
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new = old | 0x00c4; /* Bit 9 is reserved on PIIX/PIIX3. */
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else
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new = old | 0x02c4;
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if (new == old)
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return 0;
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@ -745,6 +749,8 @@ typedef struct penable {
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static const FLASH_ENABLE enables[] = {
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{0x1039, 0x0630, "SiS630", enable_flash_sis630},
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{0x8086, 0x122e, "Intel PIIX", enable_flash_piix4},
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{0x8086, 0x7000, "Intel PIIX3", enable_flash_piix4},
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{0x8086, 0x7110, "Intel PIIX4/4E/4M", enable_flash_piix4},
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{0x8086, 0x7198, "Intel 440MX", enable_flash_piix4},
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{0x8086, 0x2410, "Intel ICH", enable_flash_ich_4e},
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