lynxpoint: Add new GPIO interface for Lynxpoint-LP
The low power variant of the chipset introduces a completely new interface to the GPIOs. This is a 1KB region and so needs to be moved as well so it does not conflict with other IO regions. Also expose the gpio_get functions to ramstage and move the prototypes to pch.h so they can be used for both GPIO interfaces. Change-Id: I20bc18669525af16de8cdf99f0ccfa9612be63ad Signed-off-by: Duncan Laurie <dlaurie@chromium.org> Reviewed-on: http://review.coreboot.org/2648 Tested-by: build bot (Jenkins) Reviewed-by: Marc Jones <marc.jones@se-eng.com>
This commit is contained in:
Duncan Laurie
Stefan Reinauer
parent
51254049b9
commit
045f153a4f
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@ -45,10 +45,18 @@ smm-$(CONFIG_SPI_FLASH_SMM) += spi.c
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ramstage-$(CONFIG_HAVE_SMI_HANDLER) += smi.c
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smm-$(CONFIG_HAVE_SMI_HANDLER) += smihandler.c me_9.x.c finalize.c
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c gpio.c
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romstage-y += early_usb.c early_smbus.c early_me.c me_status.c
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romstage-$(CONFIG_USBDEBUG) += usb_debug.c
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romstage-y += reset.c early_spi.c
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ifeq ($(CONFIG_INTEL_LYNXPOINT_LP),y)
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romstage-y += lp_gpio.c
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ramstage-y += lp_gpio.c
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else
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romstage-y += gpio.c
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ramstage-y += gpio.c
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endif
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lynxpoint_add_me: $(obj)/coreboot.pre $(IFDTOOL)
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printf " DD Adding Intel Firmware Descriptor\n"
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dd if=3rdparty/mainboard/$(MAINBOARDDIR)/descriptor.bin \
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@ -194,7 +194,22 @@ Device (LPCB)
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IO (Decode16, 0xb2, 0xb2, 0x1, 0x02) // SWSMI
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//IO (Decode16, 0x800, 0x800, 0x1, 0x10) // ACPI I/O trap
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IO (Decode16, DEFAULT_PMBASE, DEFAULT_PMBASE, 0x1, 0x80) // ICH7-M ACPI
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IO (Decode16, DEFAULT_GPIOBASE, DEFAULT_GPIOBASE, 0x1, 0x40) // ICH7-M GPIO
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#if CONFIG_INTEL_LYNXPOINT_LP
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// LynxPoint LP GPIO is 1KB
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IO (Decode16, DEFAULT_GPIOBASE,
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DEFAULT_GPIOBASE, 0x1, 0xff)
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IO (Decode16, Add(DEFAULT_GPIOBASE, 0x100),
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Add(DEFAULT_GPIOBASE, 0x100), 0x1, 0xff)
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IO (Decode16, Add(DEFAULT_GPIOBASE, 0x200),
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Add(DEFAULT_GPIOBASE, 0x200), 0x1, 0xff)
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IO (Decode16, Add(DEFAULT_GPIOBASE, 0x300),
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Add(DEFAULT_GPIOBASE, 0x300), 0x1, 0xff)
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#else
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// LynxPoint GPIO is 128 bytes
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IO (Decode16, DEFAULT_GPIOBASE,
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DEFAULT_GPIOBASE, 0x1, DEFAULT_GPIOSIZE)
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#endif
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})
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}
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@ -20,16 +20,32 @@
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#ifdef __PRE_RAM__
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#include <arch/romcc_io.h>
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#else
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#include <device/device.h>
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#include <device/pci.h>
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#endif
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#include "pch.h"
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#include "gpio.h"
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#define MAX_GPIO_NUMBER 75 /* zero based */
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static u16 get_gpio_base(void)
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{
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#ifdef __PRE_RAM__
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return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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#else
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return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
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GPIO_BASE) & 0xfffc;
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#endif
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}
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void setup_pch_gpios(const struct pch_gpio_map *gpio)
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{
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u16 gpiobase = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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u16 gpiobase = get_gpio_base();
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/* GPIO Set 1 */
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if (gpio->set1.level)
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@ -69,7 +85,7 @@ void setup_pch_gpios(const struct pch_gpio_map *gpio)
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int get_gpio(int gpio_num)
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{
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static const int gpio_reg_offsets[] = {0xc, 0x38, 0x48};
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u16 gpio_base = pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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u16 gpio_base = get_gpio_base();
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int index, bit;
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if (gpio_num > MAX_GPIO_NUMBER)
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@ -20,6 +20,22 @@
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#ifndef INTEL_LYNXPOINT_GPIO_H
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#define INTEL_LYNXPOINT_GPIO_H
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/* ICH7 GPIOBASE */
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#define GPIO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_LVL 0x0c
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#define GPO_BLINK 0x18
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#define GPI_INV 0x2c
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#define GPIO_USE_SEL2 0x30
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#define GP_IO_SEL2 0x34
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#define GP_LVL2 0x38
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#define GPIO_USE_SEL3 0x40
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#define GP_IO_SEL3 0x44
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#define GP_LVL3 0x48
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#define GP_RST_SEL1 0x60
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#define GP_RST_SEL2 0x64
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#define GP_RST_SEL3 0x68
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#define GPIO_MODE_NATIVE 0
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#define GPIO_MODE_GPIO 1
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#define GPIO_MODE_NONE 1
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@ -150,12 +166,4 @@ struct pch_gpio_map {
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/* Configure GPIOs with mainboard provided settings */
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void setup_pch_gpios(const struct pch_gpio_map *gpio);
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/* get GPIO pin value */
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int get_gpio(int gpio_num);
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/*
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* get a number comprised of multiple GPIO values. gpio_num_array points to
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* the array of gpio pin numbers to scan, terminated by -1.
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*/
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unsigned get_gpios(const int *gpio_num_array);
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#endif
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@ -0,0 +1,113 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#include <stdint.h>
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#include <string.h>
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#include <arch/io.h>
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#ifdef __PRE_RAM__
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#include <arch/romcc_io.h>
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#else
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#include <device/device.h>
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#include <device/pci.h>
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#endif
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#include "pch.h"
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#include "lp_gpio.h"
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static u16 get_gpio_base(void)
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{
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#ifdef __PRE_RAM__
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return pci_read_config16(PCH_LPC_DEV, GPIO_BASE) & 0xfffc;
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#else
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return pci_read_config16(dev_find_slot(0, PCI_DEVFN(0x1f, 0)),
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GPIO_BASE) & 0xfffc;
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#endif
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}
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void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[])
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{
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u16 gpio_base = get_gpio_base();
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const struct pch_lp_gpio_map *config;
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u32 owner[3] = {0};
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u32 route[3] = {0};
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u32 irqen[3] = {0};
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u32 reset[3] = {0};
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u32 blink = 0;
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int set, bit;
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for (config = map; config->gpio != GPIO_LIST_END; config++) {
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if (config->gpio > MAX_GPIO_NUMBER)
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continue;
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/* Setup Configuration registers 1 and 2 */
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outl(config->conf0, gpio_base + GPIO_CONFIG0(config->gpio));
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outl(config->conf1, gpio_base + GPIO_CONFIG1(config->gpio));
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/* Determine set and bit based on GPIO number */
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set = config->gpio >> 5;
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bit = config->gpio % 32;
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/* Apply settings to set specific bits */
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owner[set] |= config->owner << bit;
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route[set] |= config->route << bit;
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irqen[set] |= config->irqen << bit;
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reset[set] |= config->reset << bit;
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if (set == 0)
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blink |= config->blink << bit;
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}
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for (set = 0; set <= 2; set++) {
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outl(owner[set], gpio_base + GPIO_OWNER(set));
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outl(route[set], gpio_base + GPIO_ROUTE(set));
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outl(irqen[set], gpio_base + GPIO_IRQ_IE(set));
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outl(reset[set], gpio_base + GPIO_RESET(set));
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}
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outl(blink, gpio_base + GPIO_BLINK);
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}
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int get_gpio(int gpio_num)
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{
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u16 gpio_base = get_gpio_base();
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if (gpio_num < MAX_GPIO_NUMBER)
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return 0;
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return !!(inl(gpio_base + GPIO_CONFIG0(gpio_num)) & GPI_LEVEL);
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}
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/*
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* get a number comprised of multiple GPIO values. gpio_num_array points to
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* the array of gpio pin numbers to scan, terminated by -1.
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*/
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unsigned get_gpios(const int *gpio_num_array)
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{
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int gpio;
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unsigned bitmask = 1;
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unsigned vector = 0;
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while (bitmask &&
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((gpio = *gpio_num_array++) != -1)) {
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if (get_gpio(gpio))
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vector |= bitmask;
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bitmask <<= 1;
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}
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return vector;
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}
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@ -0,0 +1,110 @@
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2012 Google Inc. All rights reserved.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*
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* You should have received a copy of the GNU General Public License
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* along with this program; if not, write to the Free Software
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* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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*/
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#ifndef INTEL_LYNXPOINT_LP_GPIO_H
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#define INTEL_LYNXPOINT_LP_GPIO_H
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/* LynxPoint LP GPIOBASE Registers */
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#define GPIO_OWNER(set) (0x00 + ((set) * 4))
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#define GPIO_PIRQ_APIC_EN 0x10
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#define GPIO_BLINK 0x18
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#define GPIO_SER_BLINK 0x1c
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#define GPIO_SER_BLINK_CS 0x20
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#define GPIO_SER_BLINK_DATA 0x24
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#define GPIO_ROUTE(set) (0x30 + ((set) * 4))
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#define GPIO_ALT_GPI_SMI_STS 0x50
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#define GPIO_ALT_GPI_SMI_EN 0x54
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#define GPIO_RESET(set) (0x60 + ((set) * 4))
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#define GPIO_GLOBAL_CONFIG 0x7c
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#define GPIO_IRQ_IS(set) (0x80 + ((set) * 4))
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#define GPIO_IRQ_IE(set) (0x90 + ((set) * 4))
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#define GPIO_CONFIG0(gpio) (0x100 + ((gpio) * 8))
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#define GPIO_CONFIG1(gpio) (0x104 + ((gpio) * 8))
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#define MAX_GPIO_NUMBER 94 /* zero based */
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#define GPIO_LIST_END 0xff
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/* conf0 */
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#define GPIO_MODE_NATIVE (0 << 0)
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#define GPIO_MODE_GPIO (1 << 0)
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#define GPIO_DIR_OUTPUT (0 << 2)
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#define GPIO_DIR_INPUT (1 << 2)
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#define GPIO_NO_INVERT (0 << 3)
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#define GPIO_INVERT (1 << 3)
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#define GPIO_IRQ_EDGE (0 << 4)
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#define GPIO_IRQ_LEVEL (1 << 4)
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#define GPI_LEVEL (1 << 30)
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#define GPO_LEVEL_LOW (0 << 31)
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#define GPO_LEVEL_HIGH (1 << 31)
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/* conf1 */
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#define GPIO_PULL_NONE (0 << 0)
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#define GPIO_PULL_DOWN (1 << 0)
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#define GPIO_PULL_UP (2 << 0)
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#define GPIO_SENSE_ENABLE (0 << 2)
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#define GPIO_SENSE_DISABLE (1 << 2)
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/* owner */
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#define GPIO_OWNER_ACPI 0
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#define GPIO_OWNER_GPIO 1
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/* route */
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#define GPIO_ROUTE_SCI 0
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#define GPIO_ROUTE_SMI 1
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/* irqen */
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#define GPIO_IRQ_DISABLE 0
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#define GPIO_IRQ_ENABLE 1
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/* blink */
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#define GPO_NO_BLINK 0
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#define GPO_BLINK 1
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/* reset */
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#define GPIO_RESET_PWROK 0
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#define GPIO_RESET_RSMRST 1
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struct pch_lp_gpio_map {
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u8 gpio;
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u32 conf0;
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u32 conf1;
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u8 owner;
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u8 route;
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u8 irqen;
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u8 reset;
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u8 blink;
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} __attribute__ ((packed));
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/* Configure GPIOs with mainboard provided settings */
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void setup_pch_lp_gpios(const struct pch_lp_gpio_map map[]);
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#endif
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@ -561,13 +561,20 @@ static void pch_lpc_read_resources(device_t dev)
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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/* GPIOBASE */
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
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res->base = DEFAULT_GPIOBASE;
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res->size = DEFAULT_GPIOSIZE;
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res->flags = IORESOURCE_IO | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, IOINDEX_SUBTRACTIVE(io_index++, 0));
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res->base = 0xff800000;
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res->size = 0x00800000; /* 8 MB for flash */
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res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
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IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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res = new_resource(dev, 3); /* IOAPIC */
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res = new_resource(dev, io_index++); /* IOAPIC */
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res->base = IO_APIC_ADDR;
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res->size = 0x00001000;
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res->flags = IORESOURCE_MEM | IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
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@ -63,10 +63,16 @@
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*/
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#define SMBUS_IO_BASE 0x0400
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#define SMBUS_SLAVE_ADDR 0x24
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/* TODO Make sure these don't get changed by stage2 */
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#define DEFAULT_GPIOBASE 0x0480
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#define DEFAULT_PMBASE 0x0500
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#if CONFIG_INTEL_LYNXPOINT_LP
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#define DEFAULT_GPIOBASE 0x1000
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#define DEFAULT_GPIOSIZE 0x400
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#else
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#define DEFAULT_GPIOBASE 0x480
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#define DEFAULT_GPIOSIZE 0x80
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#endif
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#define HPET_ADDR 0xfed00000
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#define DEFAULT_RCBA 0xfed1c000
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@ -97,6 +103,15 @@ void enable_usb_bar(void);
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int smbus_read_byte(unsigned device, unsigned address);
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int early_spi_read(u32 offset, u32 size, u8 *buffer);
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#endif
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/*
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* get GPIO pin value
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*/
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int get_gpio(int gpio_num);
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/*
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* get a number comprised of multiple GPIO values. gpio_num_array points to
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* the array of gpio pin numbers to scan, terminated by -1.
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*/
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unsigned get_gpios(const int *gpio_num_array);
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#endif
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#define MAINBOARD_POWER_OFF 0
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@ -438,22 +453,6 @@ int early_spi_read(u32 offset, u32 size, u8 *buffer);
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#define PCH_DISABLE_MEI1 (1 << 1)
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#define PCH_ENABLE_DBDF (1 << 0)
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/* ICH7 GPIOBASE */
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#define GPIO_USE_SEL 0x00
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#define GP_IO_SEL 0x04
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#define GP_LVL 0x0c
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#define GPO_BLINK 0x18
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#define GPI_INV 0x2c
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#define GPIO_USE_SEL2 0x30
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#define GP_IO_SEL2 0x34
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#define GP_LVL2 0x38
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#define GPIO_USE_SEL3 0x40
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#define GP_IO_SEL3 0x44
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#define GP_LVL3 0x48
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#define GP_RST_SEL1 0x60
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#define GP_RST_SEL2 0x64
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#define GP_RST_SEL3 0x68
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/* ICH7 PMBASE */
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#define PM1_STS 0x00
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#define WAK_STS (1 << 15)
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