purism/librem13v2: Add initial directory for librem13 v2
Add the initial directory for the port of the Librem 13 v2. The base implementation was copied from the google/chell directory and the chell references were replaced. spd directory was removed since the RAM is not soldered on the MB. The Kconfig, board_info.txt and devicetree.cb files were modified to match the Librem 13 v2 hardware information. The romstage.c, mainboard.c, Makefile.in and dsdt.asl were modified to remove chromeos specific code. The boardid.c, chromeos.c, chromeos.fmd, cmos.layout, ec.c, ec.h and smihandler.c files were removed from the tree, and the acpi directory was replaced with the acpi directory from the purism/librem13 board. These changes allow us to remove the references to chromeos specific code and allow coreboot to compile when the librem13v2 board is selected. Change-Id: I24263fde18fcea70163dbdc59df6ea1d98c97af8 Signed-off-by: Youness Alaoui <youness.alaoui@puri.sm> Reviewed-on: https://review.coreboot.org/19932 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com>
This commit is contained in:
Youness Alaoui
Martin Roth
parent
ab5b4c19c3
commit
047475cbd7
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if BOARD_PURISM_LIBREM13_V2
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config BOARD_SPECIFIC_OPTIONS # dummy
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def_bool y
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select SYSTEM_TYPE_LAPTOP
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select BOARD_ROMSIZE_KB_16384
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select DRIVERS_I2C_GENERIC
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select DRIVERS_I2C_NAU8825
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select HAVE_ACPI_RESUME
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select HAVE_ACPI_TABLES
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select SOC_INTEL_SKYLAKE
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config IRQ_SLOT_COUNT
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int
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default 18
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config MAINBOARD_VENDOR
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string
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default "Purism"
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config MAINBOARD_FAMILY
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string
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default "Librem 13"
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config MAINBOARD_PART_NUMBER
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string
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default "Librem 13 v2"
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config MAINBOARD_DIR
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string
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default "purism/librem13v2"
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config MAX_CPUS
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int
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default 8
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config NO_POST
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def_bool y
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help
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This platform does not have any way to see POST codes
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so disable them by default.
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config VGA_BIOS_ID
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string
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default "8086,1916"
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endif
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@ -0,0 +1,2 @@
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config BOARD_PURISM_LIBREM13_V2
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bool "Librem 13 v2"
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@ -0,0 +1,23 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2015 Google Inc.
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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bootblock-y += bootblock_mainboard.c
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romstage-y += pei_data.c
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ramstage-y += mainboard.c
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ramstage-y += pei_data.c
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ramstage-y += ramstage.c
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#define EC_SCI_GPI 10
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#include <ec/purism/librem/acpi/ec.asl>
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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Scope (\_SB)
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{
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Device (LID0)
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{
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Name (_HID, EisaId ("PNP0C0D"))
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Method (_STA)
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{
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Return (0xF)
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}
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Method (_LID)
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{
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Return (\_SB.PCI0.LPCB.EC.LIDS)
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}
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}
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Device (PWRB)
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{
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Name (_HID, EisaId ("PNP0C0C"))
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Method (_STA)
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{
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Return (0xF)
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}
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Name (_PRW, Package () { 27, 4 })
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}
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Device (SLPB)
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{
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Name (_HID, EisaId ("PNP0C0E"))
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Method (_STA)
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{
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Return (0xF)
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}
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}
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}
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/*
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* This file is part of the coreboot project.
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*
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* Copyright (C) 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <drivers/pc80/pc/ps2_controller.asl>
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Vendor name: Purism
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Board name: Librem 13 v2
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Board URL: https://puri.sm/librem-13/
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Category: laptop
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ROM package: SOIC8
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ROM protocol: SPI
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ROM socketed: n
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Flashrom support: y
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Release year: 2017
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/*
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* This file is part of the coreboot project.
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*
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* Copyright 2016 Google Inc.
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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* the Free Software Foundation; version 2 of the License.
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*
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* This program is distributed in the hope that it will be useful,
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* but WITHOUT ANY WARRANTY; without even the implied warranty of
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* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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* GNU General Public License for more details.
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*/
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#include <bootblock_common.h>
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#include <soc/gpio.h>
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#include "gpio.h"
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static void early_config_gpio(void)
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{
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/* This is a hack for FSP because it does things in MemoryInit()
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* which it shouldn't do. We have to prepare certain gpios here
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* because of the brokenness in FSP. */
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gpio_configure_pads(early_gpio_table, ARRAY_SIZE(early_gpio_table));
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}
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void bootblock_mainboard_init(void)
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{
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early_config_gpio();
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}
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chip soc/intel/skylake
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# Enable deep Sx states
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register "deep_s3_enable_ac" = "0"
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register "deep_s3_enable_dc" = "0"
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register "deep_s5_enable_ac" = "1"
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register "deep_s5_enable_dc" = "1"
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register "deep_sx_config" = "DSX_EN_LAN_WAKE_PIN"
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# GPE configuration
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# Note that GPE events called out in ASL code rely on this
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# route. i.e. If this route changes then the affected GPE
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# offset bits also need to be changed.
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register "gpe0_dw0" = "GPP_B"
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register "gpe0_dw1" = "GPP_D"
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register "gpe0_dw2" = "GPP_E"
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# EC host command ranges are in 0x800-0x8ff & 0x200-0x20f
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register "gen1_dec" = "0x00fc0801"
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register "gen2_dec" = "0x000c0201"
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# Enable "Intel Speed Shift Technology"
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register "speed_shift_enable" = "1"
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# Enable DPTF
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register "dptf_enable" = "1"
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# FSP Configuration
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register "ProbelessTrace" = "0"
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register "EnableLan" = "0"
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register "EnableSata" = "0"
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register "SataSalpSupport" = "0"
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register "SataMode" = "0"
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register "SataPortsEnable[0]" = "0"
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register "EnableAzalia" = "1"
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register "DspEnable" = "1"
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register "IoBufferOwnership" = "3"
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register "EnableTraceHub" = "0"
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register "XdciEnable" = "0"
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register "SsicPortEnable" = "0"
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register "SmbusEnable" = "1"
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register "Cio2Enable" = "0"
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register "ScsEmmcEnabled" = "1"
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register "ScsEmmcHs400Enabled" = "1"
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register "ScsSdCardEnabled" = "0"
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register "IshEnable" = "0"
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register "PttSwitch" = "0"
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register "InternalGfx" = "1"
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register "SkipExtGfxScan" = "1"
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register "Device4Enable" = "1"
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register "HeciEnabled" = "0"
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register "FspSkipMpInit" = "1"
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register "SaGv" = "3"
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register "SerialIrqConfigSirqEnable" = "1"
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register "PmConfigSlpS3MinAssert" = "2" # 50ms
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register "PmConfigSlpS4MinAssert" = "1" # 1s
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register "PmConfigSlpSusMinAssert" = "1" # 500ms
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register "PmConfigSlpAMinAssert" = "3" # 2s
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register "PmTimerDisabled" = "1"
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register "pirqa_routing" = "PCH_IRQ11"
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register "pirqb_routing" = "PCH_IRQ10"
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register "pirqc_routing" = "PCH_IRQ11"
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register "pirqd_routing" = "PCH_IRQ11"
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register "pirqe_routing" = "PCH_IRQ11"
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register "pirqf_routing" = "PCH_IRQ11"
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register "pirqg_routing" = "PCH_IRQ11"
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register "pirqh_routing" = "PCH_IRQ11"
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# VR Settings Configuration for 5 Domains
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Domain/Setting | SA | IA | Ring Sliced | GT Unsliced | GT |
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#+----------------+-------+-------+-------------+-------------+-------+
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#| Psi1Threshold | 20A | 20A | 20A | 20A | 20A |
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#| Psi2Threshold | 4A | 5A | 5A | 5A | 5A |
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#| Psi3Threshold | 1A | 1A | 1A | 1A | 1A |
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#| Psi3Enable | 1 | 1 | 1 | 1 | 1 |
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#| Psi4Enable | 1 | 1 | 1 | 1 | 1 |
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#| ImonSlope | 0 | 0 | 0 | 0 | 0 |
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#| ImonOffset | 0 | 0 | 0 | 0 | 0 |
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#| IccMax | 7A | 34A | 34A | 35A | 35A |
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#| VrVoltageLimit | 1.52V | 1.52V | 1.52V | 1.52V | 1.52V |
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#+----------------+-------+-------+-------------+-------------+-------+
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register "domain_vr_config[VR_SYSTEM_AGENT]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(4),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(7),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_IA_CORE]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_RING]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(34),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_UNSLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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register "domain_vr_config[VR_GT_SLICED]" = "{
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.vr_config_enable = 1,
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.psi1threshold = VR_CFG_AMP(20),
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.psi2threshold = VR_CFG_AMP(5),
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.psi3threshold = VR_CFG_AMP(1),
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.psi3enable = 1,
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.psi4enable = 1,
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.imon_slope = 0x0,
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.imon_offset = 0x0,
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.icc_max = VR_CFG_AMP(35),
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.voltage_limit = 1520,
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}"
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# Enable Root port 1.
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register "PcieRpEnable[0]" = "1"
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# Enable CLKREQ#
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register "PcieRpClkReqSupport[0]" = "1"
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# RP 1 uses SRCCLKREQ1#
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register "PcieRpClkReqNumber[0]" = "1"
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||||||
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register "usb2_ports[0]" = "USB2_PORT_LONG(OC2)" # Type-C Port 1
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||||||
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register "usb2_ports[1]" = "USB2_PORT_LONG(OC3)" # Type-C Port 2
|
||||||
|
register "usb2_ports[2]" = "USB2_PORT_MID(OC_SKIP)" # Bluetooth
|
||||||
|
register "usb2_ports[4]" = "USB2_PORT_MID(OC0)" # Type-A Port
|
||||||
|
register "usb2_ports[6]" = "USB2_PORT_FLEX(OC_SKIP)" # Camera
|
||||||
|
register "usb2_ports[8]" = "USB2_PORT_MID(OC_SKIP)" # SD
|
||||||
|
|
||||||
|
register "usb3_ports[0]" = "USB3_PORT_DEFAULT(OC2)" # Type-C Port 1
|
||||||
|
register "usb3_ports[1]" = "USB3_PORT_DEFAULT(OC3)" # Type-C Port 2
|
||||||
|
register "usb3_ports[2]" = "USB3_PORT_DEFAULT(OC0)" # Type-A Port
|
||||||
|
register "usb3_ports[3]" = "USB3_PORT_DEFAULT(OC_SKIP)" # SD
|
||||||
|
|
||||||
|
register "i2c_voltage[4]" = "I2C_VOLTAGE_1V8" # I2C4 is 1.8V
|
||||||
|
|
||||||
|
# Must leave UART0 enabled or SD/eMMC will not work as PCI
|
||||||
|
register "SerialIoDevMode" = "{
|
||||||
|
[PchSerialIoIndexI2C0] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C1] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C2] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexI2C3] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexI2C4] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexI2C5] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexSpi0] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexSpi1] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexUart0] = PchSerialIoPci,
|
||||||
|
[PchSerialIoIndexUart1] = PchSerialIoDisabled,
|
||||||
|
[PchSerialIoIndexUart2] = PchSerialIoSkipInit,
|
||||||
|
}"
|
||||||
|
|
||||||
|
# PL2 override 15W
|
||||||
|
register "tdp_pl2_override" = "15"
|
||||||
|
|
||||||
|
register "tcc_offset" = "10" # TCC of 90C
|
||||||
|
|
||||||
|
# Send an extra VR mailbox command for the supported MPS IMVP8 model
|
||||||
|
register "SendVrMbxCmd" = "1"
|
||||||
|
|
||||||
|
device cpu_cluster 0 on
|
||||||
|
device lapic 0 on end
|
||||||
|
end
|
||||||
|
device domain 0 on
|
||||||
|
device pci 00.0 on end # Host Bridge
|
||||||
|
device pci 02.0 on end # Integrated Graphics Device
|
||||||
|
device pci 14.0 on end # USB xHCI
|
||||||
|
device pci 14.1 off end # USB xDCI (OTG)
|
||||||
|
device pci 14.2 on end # Thermal Subsystem
|
||||||
|
device pci 16.0 on end # Management Engine Interface 1
|
||||||
|
device pci 16.1 off end # Management Engine Interface 2
|
||||||
|
device pci 16.2 off end # Management Engine IDE-R
|
||||||
|
device pci 16.3 off end # Management Engine KT Redirection
|
||||||
|
device pci 16.4 off end # Management Engine Interface 3
|
||||||
|
device pci 17.0 on end # SATA
|
||||||
|
device pci 1c.0 on
|
||||||
|
chip drivers/intel/wifi
|
||||||
|
register "wake" = "GPE0_DW0_16"
|
||||||
|
device pci 00.0 on end
|
||||||
|
end
|
||||||
|
end # PCI Express Port 1
|
||||||
|
device pci 1c.1 off end # PCI Express Port 2
|
||||||
|
device pci 1c.2 off end # PCI Express Port 3
|
||||||
|
device pci 1c.3 off end # PCI Express Port 4
|
||||||
|
device pci 1c.4 off end # PCI Express Port 5
|
||||||
|
device pci 1c.5 off end # PCI Express Port 6
|
||||||
|
device pci 1c.6 off end # PCI Express Port 7
|
||||||
|
device pci 1c.7 off end # PCI Express Port 8
|
||||||
|
device pci 1d.0 off end # PCI Express Port 9
|
||||||
|
device pci 1d.1 off end # PCI Express Port 10
|
||||||
|
device pci 1d.2 off end # PCI Express Port 11
|
||||||
|
device pci 1d.3 off end # PCI Express Port 12
|
||||||
|
device pci 1f.0 on
|
||||||
|
chip ec/purism/librem
|
||||||
|
device pnp 0c09.0 on end
|
||||||
|
end
|
||||||
|
end # LPC Interface
|
||||||
|
device pci 1f.1 off end # P2SB
|
||||||
|
device pci 1f.2 on end # Power Management Controller
|
||||||
|
device pci 1f.3 on end # Intel HDA
|
||||||
|
device pci 1f.4 on end # SMBus
|
||||||
|
device pci 1f.5 on end # PCH SPI
|
||||||
|
device pci 1f.6 off end # GbE
|
||||||
|
end
|
||||||
|
end
|
||||||
|
|
@ -0,0 +1,50 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2015 Google Inc.
|
||||||
|
* Copyright (C) 2015 Intel Corporation
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
DefinitionBlock(
|
||||||
|
"dsdt.aml",
|
||||||
|
"DSDT",
|
||||||
|
0x05, // DSDT revision: ACPI v5.0
|
||||||
|
"COREv4", // OEM id
|
||||||
|
"COREBOOT", // OEM table id
|
||||||
|
0x20110725 // OEM revision
|
||||||
|
)
|
||||||
|
{
|
||||||
|
// Some generic macros
|
||||||
|
#include <soc/intel/skylake/acpi/platform.asl>
|
||||||
|
|
||||||
|
// global NVS and variables
|
||||||
|
#include <soc/intel/skylake/acpi/globalnvs.asl>
|
||||||
|
|
||||||
|
// CPU
|
||||||
|
#include <soc/intel/skylake/acpi/cpu.asl>
|
||||||
|
|
||||||
|
Scope (\_SB) {
|
||||||
|
Device (PCI0)
|
||||||
|
{
|
||||||
|
#include <soc/intel/skylake/acpi/systemagent.asl>
|
||||||
|
#include <soc/intel/skylake/acpi/pch.asl>
|
||||||
|
}
|
||||||
|
|
||||||
|
}
|
||||||
|
|
||||||
|
// Chipset specific sleep states
|
||||||
|
#include <soc/intel/skylake/acpi/sleepstates.asl>
|
||||||
|
|
||||||
|
// Mainboard specific
|
||||||
|
#include "acpi/mainboard.asl"
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,252 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2015 Google Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#ifndef MAINBOARD_GPIO_H
|
||||||
|
#define MAINBOARD_GPIO_H
|
||||||
|
|
||||||
|
#include <soc/gpe.h>
|
||||||
|
#include <soc/gpio.h>
|
||||||
|
|
||||||
|
/* EC in RW */
|
||||||
|
#define GPIO_EC_IN_RW GPP_C6
|
||||||
|
|
||||||
|
/* BIOS Flash Write Protect */
|
||||||
|
#define GPIO_PCH_WP GPP_C23
|
||||||
|
|
||||||
|
/* Memory configuration board straps */
|
||||||
|
#define GPIO_MEM_CONFIG_0 GPP_C12
|
||||||
|
#define GPIO_MEM_CONFIG_1 GPP_C13
|
||||||
|
#define GPIO_MEM_CONFIG_2 GPP_C14
|
||||||
|
#define GPIO_MEM_CONFIG_3 GPP_C15
|
||||||
|
|
||||||
|
/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
|
||||||
|
#define GPE_EC_WAKE GPE0_LAN_WAK
|
||||||
|
|
||||||
|
/* GPP_B16 is WLAN_WAKE. GPP_B group is routed to DW0 in the GPE0 block */
|
||||||
|
#define GPE_WLAN_WAKE GPE0_DW0_16
|
||||||
|
|
||||||
|
/* GPP_B5 is TOUCHPAD WAKE. GPP_B group is routed to DW0 in the GPE0 block */
|
||||||
|
#define GPE_TOUCHPAD_WAKE GPE0_DW0_05
|
||||||
|
|
||||||
|
/* Input device interrupt configuration */
|
||||||
|
#define TOUCHPAD_INT_L GPP_B3_IRQ
|
||||||
|
#define TOUCHSCREEN_INT_L GPP_E7_IRQ
|
||||||
|
#define MIC_INT_L GPP_F10_IRQ
|
||||||
|
|
||||||
|
/* GPP_E16 is EC_SCI_L. GPP_E group is routed to DW2 in the GPE0 block */
|
||||||
|
#define EC_SCI_GPI GPE0_DW2_16
|
||||||
|
#define EC_SMI_GPI GPP_E15
|
||||||
|
|
||||||
|
/* Power rail control signals. */
|
||||||
|
#define EN_PP3300_KEPLER GPP_C11
|
||||||
|
#define EN_PP3300_DX_TOUCH GPP_C22
|
||||||
|
#define EN_PP3300_DX_EMMC GPP_D5
|
||||||
|
#define EN_PP1800_DX_EMMC GPP_D6
|
||||||
|
#define EN_PP3300_DX_CAM GPP_D12
|
||||||
|
|
||||||
|
#ifndef __ACPI__
|
||||||
|
/* Pad configuration in ramstage. */
|
||||||
|
static const struct pad_config gpio_table[] = {
|
||||||
|
/* RCIN# */ PAD_CFG_NF(GPP_A0, NONE, DEEP, NF1),
|
||||||
|
/* LAD0 */ PAD_CFG_NF(GPP_A1, 20K_PU, DEEP, NF1),
|
||||||
|
/* LAD1 */ PAD_CFG_NF(GPP_A2, 20K_PU, DEEP, NF1),
|
||||||
|
/* LAD2 */ PAD_CFG_NF(GPP_A3, 20K_PU, DEEP, NF1),
|
||||||
|
/* LAD3 */ PAD_CFG_NF(GPP_A4, 20K_PU, DEEP, NF1),
|
||||||
|
/* LFRAME# */ PAD_CFG_NF(GPP_A5, NONE, DEEP, NF1),
|
||||||
|
/* SERIRQ */ PAD_CFG_NF(GPP_A6, NONE, DEEP, NF1),
|
||||||
|
/* PIRQA# */ PAD_CFG_NC(GPP_A7),
|
||||||
|
/* CLKRUN# */ PAD_CFG_NF(GPP_A8, NONE, DEEP, NF1),
|
||||||
|
/* CLKOUT_LPC0 */ PAD_CFG_NF(GPP_A9, NONE, DEEP, NF1),
|
||||||
|
/* CLKOUT_LPC1 */ PAD_CFG_NC(GPP_A10),
|
||||||
|
/* PME# */ PAD_CFG_GPO(GPP_A11, 0, DEEP),
|
||||||
|
/* BM_BUSY# */ PAD_CFG_NC(GPP_A12),
|
||||||
|
/* SUSWARN# */ PAD_CFG_NF(GPP_A13, NONE, DEEP, NF1),
|
||||||
|
/* SUS_STAT# */ PAD_CFG_GPO(GPP_A14, 0, DEEP),
|
||||||
|
/* SUSACK# */ PAD_CFG_NF(GPP_A15, NONE, DEEP, NF1),
|
||||||
|
/* SD_1P8_SEL */ PAD_CFG_NC(GPP_A16),
|
||||||
|
/* SD_PWR_EN# */ PAD_CFG_NC(GPP_A17),
|
||||||
|
/* ISH_GP0 */ PAD_CFG_NC(GPP_A18),
|
||||||
|
/* ISH_GP1 */ PAD_CFG_NC(GPP_A19),
|
||||||
|
/* ISH_GP2 */ PAD_CFG_NC(GPP_A20),
|
||||||
|
/* ISH_GP3 */ PAD_CFG_NC(GPP_A21),
|
||||||
|
/* ISH_GP4 */ PAD_CFG_NC(GPP_A22),
|
||||||
|
/* ISH_GP5 */ PAD_CFG_NC(GPP_A23),
|
||||||
|
/* CORE_VID0 */ PAD_CFG_GPO(GPP_B0, 0, DEEP),
|
||||||
|
/* CORE_VID1 */ PAD_CFG_GPO(GPP_B1, 0, DEEP),
|
||||||
|
/* VRALERT# */ PAD_CFG_NC(GPP_B2),
|
||||||
|
/* CPU_GP2 */ PAD_CFG_GPI_APIC(GPP_B3, NONE, PLTRST),
|
||||||
|
/* TRACKPAD_INT_L */
|
||||||
|
/* CPU_GP3 */ PAD_CFG_GPO(GPP_B4, 1, DEEP), /* TOUCHSCREEN_EN */
|
||||||
|
/* SRCCLKREQ0# */ PAD_CFG_GPI_ACPI_SCI(GPP_B5, NONE, DEEP, YES),
|
||||||
|
/* TRACKPAD WAKE */
|
||||||
|
/* SRCCLKREQ1# */ PAD_CFG_NF(GPP_B6, NONE, DEEP, NF1), /* WLAN CKLREQ */
|
||||||
|
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER CLKREQ */
|
||||||
|
/* SRCCLKREQ3# */ PAD_CFG_NC(GPP_B8),
|
||||||
|
/* SRCCLKREQ4# */ PAD_CFG_NC(GPP_B9),
|
||||||
|
/* SRCCLKREQ5# */ PAD_CFG_NC(GPP_B10),
|
||||||
|
/* EXT_PWR_GATE# */ PAD_CFG_NC(GPP_B11),
|
||||||
|
/* SLP_S0# */ PAD_CFG_NF(GPP_B12, NONE, DEEP, NF1),
|
||||||
|
/* PLTRST# */ PAD_CFG_NF(GPP_B13, NONE, DEEP, NF1),
|
||||||
|
/* SPKR */ PAD_CFG_GPO(GPP_B14, 0, DEEP),
|
||||||
|
/* GSPI0_CS# */ PAD_CFG_NC(GPP_B15),
|
||||||
|
/* GSPI0_CLK */ PAD_CFG_GPI_ACPI_SCI(GPP_B16, NONE, DEEP, YES),
|
||||||
|
/* WLAN WAKE */
|
||||||
|
/* GSPI0_MISO */ PAD_CFG_NC(GPP_B17),
|
||||||
|
/* GSPI0_MOSI */ PAD_CFG_GPO(GPP_B18, 0, DEEP),
|
||||||
|
/* GSPI1_CS# */ PAD_CFG_NC(GPP_B19),
|
||||||
|
/* GSPI1_CLK */ PAD_CFG_NC(GPP_B20),
|
||||||
|
/* GSPI1_MISO */ PAD_CFG_NC(GPP_B21),
|
||||||
|
/* GSPI1_MOSI */ PAD_CFG_GPO(GPP_B22, 0, DEEP),
|
||||||
|
/* SM1ALERT# */ PAD_CFG_GPI(GPP_B23, NONE, DEEP), /* UNUSED */
|
||||||
|
/* SMBCLK */ PAD_CFG_NF(GPP_C0, NONE, DEEP, NF1), /* XDP */
|
||||||
|
/* SMBDATA */ PAD_CFG_NF(GPP_C1, NONE, DEEP, NF1), /* XDP */
|
||||||
|
/* SMBALERT# */ PAD_CFG_GPO(GPP_C2, 0, DEEP),
|
||||||
|
/* SML0CLK */ PAD_CFG_GPI(GPP_C3, NONE, DEEP), /* UNUSED */
|
||||||
|
/* SML0DATA */ PAD_CFG_GPI(GPP_C4, NONE, DEEP), /* UNUSED */
|
||||||
|
/* SML0ALERT# */ PAD_CFG_GPI(GPP_C5, NONE, DEEP), /* UNUSED */
|
||||||
|
/* SM1CLK */ PAD_CFG_GPI(GPP_C6, 20K_PU, DEEP), /* EC_IN_RW */
|
||||||
|
/* SM1DATA */ PAD_CFG_GPI(GPP_C7, NONE, DEEP), /* UNUSED */
|
||||||
|
/* UART0_RXD */ PAD_CFG_NC(GPP_C8),
|
||||||
|
/* UART0_TXD */ PAD_CFG_NC(GPP_C9),
|
||||||
|
/* UART0_RTS# */ PAD_CFG_NC(GPP_C10),
|
||||||
|
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
|
||||||
|
/* UART1_RXD */ PAD_CFG_GPI(GPP_C12, NONE, DEEP), /* MEM_CONFIG[0] */
|
||||||
|
/* UART1_TXD */ PAD_CFG_GPI(GPP_C13, NONE, DEEP), /* MEM_CONFIG[1] */
|
||||||
|
/* UART1_RTS# */ PAD_CFG_GPI(GPP_C14, NONE, DEEP), /* MEM_CONFIG[2] */
|
||||||
|
/* UART1_CTS# */ PAD_CFG_GPI(GPP_C15, NONE, DEEP), /* MEM_CONFIG[3] */
|
||||||
|
/* I2C0_SDA */ PAD_CFG_NF(GPP_C16, NONE, DEEP, NF1), /* TOUCHSCREEN */
|
||||||
|
/* I2C0_SCL */ PAD_CFG_NF(GPP_C17, NONE, DEEP, NF1), /* TOUCHSCREEN */
|
||||||
|
/* I2C1_SDA */ PAD_CFG_NF(GPP_C18, NONE, DEEP, NF1), /* TRACKPAD */
|
||||||
|
/* I2C1_SCL */ PAD_CFG_NF(GPP_C19, NONE, DEEP, NF1), /* TRACKPAD */
|
||||||
|
/* UART2_RXD */ PAD_CFG_NF(GPP_C20, NONE, DEEP, NF1), /* SERVO */
|
||||||
|
/* UART2_TXD */ PAD_CFG_NF(GPP_C21, NONE, DEEP, NF1), /* SERVO */
|
||||||
|
/* UART2_RTS# */ PAD_CFG_GPO(GPP_C22, 1, DEEP), /* EN_PP3300_DX_TOUCH */
|
||||||
|
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
|
||||||
|
/* SPI1_CS# */ PAD_CFG_GPO(GPP_D0, 0, DEEP),
|
||||||
|
/* SPI1_CLK */ PAD_CFG_GPO(GPP_D1, 0, DEEP),
|
||||||
|
/* SPI1_MISO */ PAD_CFG_GPO(GPP_D2, 0, DEEP),
|
||||||
|
/* SPI1_MOSI */ PAD_CFG_GPO(GPP_D3, 0, DEEP),
|
||||||
|
/* FASHTRIG */ PAD_CFG_NC(GPP_D4),
|
||||||
|
/* ISH_I2C0_SDA */ PAD_CFG_GPO(GPP_D5, 1, DEEP), /* EN_PP3300_DX_EMMC */
|
||||||
|
/* ISH_I2C0_SCL */ PAD_CFG_GPO(GPP_D6, 1, DEEP), /* EN_PP1800_DX_EMMC */
|
||||||
|
/* ISH_I2C1_SDA */ PAD_CFG_NC(GPP_D7),
|
||||||
|
/* ISH_I2C1_SCL */ PAD_CFG_NC(GPP_D8),
|
||||||
|
/* ISH_SPI_CS# */ PAD_CFG_NC(GPP_D9),
|
||||||
|
/* ISH_SPI_CLK */ PAD_CFG_GPO(GPP_D10, 0, DEEP), /* USBA_1_ILIM_SEL_L */
|
||||||
|
/* ISH_SPI_MISO */ PAD_CFG_NC(GPP_D11),
|
||||||
|
/* ISH_SPI_MOSI */ PAD_CFG_GPO(GPP_D12, 1, DEEP), /* EN_PP3300_DX_CAM */
|
||||||
|
/* ISH_UART0_RXD */ PAD_CFG_NC(GPP_D13),
|
||||||
|
/* ISH_UART0_TXD */ PAD_CFG_NC(GPP_D14),
|
||||||
|
/* ISH_UART0_RTS# */ PAD_CFG_NC(GPP_D15),
|
||||||
|
/* ISH_UART0_CTS# */ PAD_CFG_NC(GPP_D16),
|
||||||
|
/* DMIC_CLK1 */ PAD_CFG_NC(GPP_D17),
|
||||||
|
/* DMIC_DATA1 */ PAD_CFG_NC(GPP_D18),
|
||||||
|
/* DMIC_CLK0 */ PAD_CFG_NF(GPP_D19, NONE, DEEP, NF1),
|
||||||
|
/* DMIC_DATA0 */ PAD_CFG_NF(GPP_D20, NONE, DEEP, NF1),
|
||||||
|
/* SPI1_IO2 */ PAD_CFG_GPO(GPP_D21, 0, DEEP),
|
||||||
|
/* SPI1_IO3 */ PAD_CFG_GPO(GPP_D22, 0, DEEP), /* I2S2 BUFFER */
|
||||||
|
/* I2S_MCLK */ PAD_CFG_NF(GPP_D23, NONE, DEEP, NF1),
|
||||||
|
/* SATAXPCI0 */ PAD_CFG_GPI_APIC(GPP_E0, NONE, PLTRST), /* TPM_PIRQ_L */
|
||||||
|
/* SATAXPCIE1 */ PAD_CFG_NC(GPP_E1),
|
||||||
|
/* SATAXPCIE2 */ PAD_CFG_NC(GPP_E2),
|
||||||
|
/* CPU_GP0 */ PAD_CFG_GPO(GPP_E3, 1, DEEP), /* TOUCHSCREEN_RST_L */
|
||||||
|
/* SATA_DEVSLP0 */ PAD_CFG_NC(GPP_E4),
|
||||||
|
/* SATA_DEVSLP1 */ PAD_CFG_NC(GPP_E5),
|
||||||
|
/* SATA_DEVSLP2 */ PAD_CFG_NC(GPP_E6),
|
||||||
|
/* CPU_GP1 */ PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST),
|
||||||
|
/* TOUCHSCREEN_INT_L */
|
||||||
|
/* SATALED# */ PAD_CFG_NC(GPP_E8),
|
||||||
|
/* USB2_OCO# */ PAD_CFG_NF(GPP_E9, NONE, DEEP, NF1), /* USBA_OC0_L */
|
||||||
|
/* USB2_OC1# */ PAD_CFG_NC(GPP_E10),
|
||||||
|
/* USB2_OC2# */ PAD_CFG_NF(GPP_E11, NONE, DEEP, NF1), /* USBC_OC2_L */
|
||||||
|
/* USB2_OC3# */ PAD_CFG_NF(GPP_E12, NONE, DEEP, NF1), /* USBC_OC3_L */
|
||||||
|
/* DDPB_HPD0 */ PAD_CFG_NF(GPP_E13, NONE, DEEP, NF1),
|
||||||
|
/* USB_C0_DP_HPD */
|
||||||
|
/* DDPC_HPD1 */ PAD_CFG_NF(GPP_E14, NONE, DEEP, NF1),
|
||||||
|
/* USB_C1_DP_HPD */
|
||||||
|
/* DDPD_HPD2 */ PAD_CFG_GPI_ACPI_SMI(GPP_E15, NONE, DEEP, YES),
|
||||||
|
/* EC_SMI_L */
|
||||||
|
/* DDPE_HPD3 */ PAD_CFG_GPI_ACPI_SCI(GPP_E16, NONE, DEEP, YES),
|
||||||
|
/* EC_SCI_L */
|
||||||
|
/* EDP_HPD */ PAD_CFG_NF(GPP_E17, NONE, DEEP, NF1),
|
||||||
|
/* DDPB_CTRLCLK */ PAD_CFG_GPO(GPP_E18, 0, DEEP),
|
||||||
|
/* DDPB_CTRLDATA */ PAD_CFG_NC(GPP_E19), /* External pullup */
|
||||||
|
/* DDPC_CTRLCLK */ PAD_CFG_NC(GPP_E20),
|
||||||
|
/* DDPC_CTRLDATA */ PAD_CFG_NC(GPP_E21), /* External pullup. */
|
||||||
|
/* DDPD_CTRLCLK */ PAD_CFG_NC(GPP_E22),
|
||||||
|
/* DDPD_CTRLDATA */ PAD_CFG_NC(GPP_E23),
|
||||||
|
/*
|
||||||
|
* The next 4 pads are for bit banging the amplifiers. They are connected
|
||||||
|
* together with i2s0 signals. For default behavior of i2s make these
|
||||||
|
* gpio inupts.
|
||||||
|
*/
|
||||||
|
/* I2S2_SCLK */ PAD_CFG_GPI(GPP_F0, NONE, DEEP),
|
||||||
|
/* I2S2_SFRM */ PAD_CFG_GPI(GPP_F1, NONE, DEEP),
|
||||||
|
/* I2S2_TXD */ PAD_CFG_GPI(GPP_F2, NONE, DEEP),
|
||||||
|
/* I2S2_RXD */ PAD_CFG_GPI(GPP_F3, NONE, DEEP),
|
||||||
|
/* I2C2_SDA */ PAD_CFG_NC(GPP_F4),
|
||||||
|
/* I2C2_SCL */ PAD_CFG_NC(GPP_F5),
|
||||||
|
/* I2C3_SDA */ PAD_CFG_NC(GPP_F6),
|
||||||
|
/* I2C3_SCL */ PAD_CFG_NC(GPP_F7),
|
||||||
|
/* I2C4_SDA */ PAD_CFG_NF_1V8(GPP_F8, NONE, DEEP, NF1),
|
||||||
|
/* AUDIO1V8_SDA */
|
||||||
|
/* I2C4_SCL */ PAD_CFG_NF_1V8(GPP_F9, NONE, DEEP, NF1),
|
||||||
|
/* AUDIO1V8_SCL */
|
||||||
|
/* I2C5_SDA */ PAD_CFG_GPI_APIC(GPP_F10, NONE, PLTRST), /* MIC_INT_L */
|
||||||
|
/* I2C5_SCL */ PAD_CFG_GPO(GPP_F11, 0, DEEP),
|
||||||
|
/* EMMC_CMD */ PAD_CFG_NF(GPP_F12, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA0 */ PAD_CFG_NF(GPP_F13, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA1 */ PAD_CFG_NF(GPP_F14, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA2 */ PAD_CFG_NF(GPP_F15, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA3 */ PAD_CFG_NF(GPP_F16, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA4 */ PAD_CFG_NF(GPP_F17, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA5 */ PAD_CFG_NF(GPP_F18, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA6 */ PAD_CFG_NF(GPP_F19, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_DATA7 */ PAD_CFG_NF(GPP_F20, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_RCLK */ PAD_CFG_NF(GPP_F21, NONE, DEEP, NF1),
|
||||||
|
/* EMMC_CLK */ PAD_CFG_NF(GPP_F22, NONE, DEEP, NF1),
|
||||||
|
/* RSVD */ PAD_CFG_NC(GPP_F23),
|
||||||
|
/* SD_CMD */ PAD_CFG_NC(GPP_G0),
|
||||||
|
/* SD_DATA0 */ PAD_CFG_NC(GPP_G1),
|
||||||
|
/* SD_DATA1 */ PAD_CFG_NC(GPP_G2),
|
||||||
|
/* SD_DATA2 */ PAD_CFG_NC(GPP_G3),
|
||||||
|
/* SD_DATA3 */ PAD_CFG_NC(GPP_G4),
|
||||||
|
/* SD_CD# */ PAD_CFG_NC(GPP_G5),
|
||||||
|
/* SD_CLK */ PAD_CFG_NC(GPP_G6),
|
||||||
|
/* SD_WP */ PAD_CFG_NC(GPP_G7),
|
||||||
|
/* BATLOW# */ PAD_CFG_NF(GPD0, NONE, DEEP, NF1),
|
||||||
|
/* ACPRESENT */ PAD_CFG_NF(GPD1, NONE, DEEP, NF1),
|
||||||
|
/* LAN_WAKE# */ PAD_CFG_NF(GPD2, NONE, DEEP, NF1), /* EC_PCH_WAKE_L */
|
||||||
|
/* PWRBTN# */ PAD_CFG_NF(GPD3, NONE, DEEP, NF1),
|
||||||
|
/* SLP_S3# */ PAD_CFG_NF(GPD4, NONE, DEEP, NF1),
|
||||||
|
/* SLP_S4# */ PAD_CFG_NF(GPD5, NONE, DEEP, NF1),
|
||||||
|
/* SLP_A# */ PAD_CFG_GPO(GPD6, 0, DEEP),
|
||||||
|
/* RSVD */ PAD_CFG_NC(GPD7),
|
||||||
|
/* SUSCLK */ PAD_CFG_NF(GPD8, NONE, DEEP, NF1),
|
||||||
|
/* SLP_WLAN# */ PAD_CFG_GPO(GPD9, 0, DEEP),
|
||||||
|
/* SLP_S5# */ PAD_CFG_GPO(GPD10, 0, DEEP),
|
||||||
|
/* LANPHYC */ PAD_CFG_NC(GPD11),
|
||||||
|
};
|
||||||
|
|
||||||
|
/* Early pad configuration in romstage. */
|
||||||
|
static const struct pad_config early_gpio_table[] = {
|
||||||
|
/* SRCCLKREQ2# */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* KEPLER */
|
||||||
|
/* UART0_CTS# */ PAD_CFG_GPO(GPP_C11, 0, DEEP), /* EN_PP3300_KEPLER */
|
||||||
|
/* UART2_CTS# */ PAD_CFG_GPI(GPP_C23, 20K_PU, DEEP), /* PCH_WP */
|
||||||
|
};
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
||||||
|
#endif
|
||||||
|
|
@ -0,0 +1,69 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007-2009 coresystems GmbH
|
||||||
|
* Copyright (C) 2015 Google Inc.
|
||||||
|
* Copyright (C) 2015 Intel Corporation
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <arch/acpi.h>
|
||||||
|
#include <console/console.h>
|
||||||
|
#include <device/device.h>
|
||||||
|
#include <stdlib.h>
|
||||||
|
#include <soc/nhlt.h>
|
||||||
|
|
||||||
|
static unsigned long mainboard_write_acpi_tables(
|
||||||
|
device_t device, unsigned long current, acpi_rsdp_t *rsdp)
|
||||||
|
{
|
||||||
|
uintptr_t start_addr;
|
||||||
|
uintptr_t end_addr;
|
||||||
|
struct nhlt *nhlt;
|
||||||
|
|
||||||
|
start_addr = current;
|
||||||
|
|
||||||
|
nhlt = nhlt_init();
|
||||||
|
|
||||||
|
if (nhlt == NULL)
|
||||||
|
return start_addr;
|
||||||
|
|
||||||
|
/* 2 Channel DMIC array. */
|
||||||
|
if (nhlt_soc_add_dmic_array(nhlt, 2))
|
||||||
|
printk(BIOS_ERR, "Couldn't add 2CH DMIC array.\n");
|
||||||
|
|
||||||
|
/* ADI Smart Amps for left and right. */
|
||||||
|
if (nhlt_soc_add_ssm4567(nhlt, AUDIO_LINK_SSP0))
|
||||||
|
printk(BIOS_ERR, "Couldn't add ssm4567.\n");
|
||||||
|
|
||||||
|
/* NAU88l25 Headset codec. */
|
||||||
|
if (nhlt_soc_add_nau88l25(nhlt, AUDIO_LINK_SSP1))
|
||||||
|
printk(BIOS_ERR, "Couldn't add headset codec.\n");
|
||||||
|
|
||||||
|
end_addr = nhlt_soc_serialize(nhlt, start_addr);
|
||||||
|
|
||||||
|
if (end_addr != start_addr)
|
||||||
|
acpi_add_table(rsdp, (void *)start_addr);
|
||||||
|
|
||||||
|
return end_addr;
|
||||||
|
}
|
||||||
|
|
||||||
|
/*
|
||||||
|
* mainboard_enable is executed as first thing after
|
||||||
|
* enumerate_buses().
|
||||||
|
*/
|
||||||
|
static void mainboard_enable(device_t dev)
|
||||||
|
{
|
||||||
|
dev->ops->write_acpi_tables = mainboard_write_acpi_tables;
|
||||||
|
}
|
||||||
|
|
||||||
|
struct chip_operations mainboard_ops = {
|
||||||
|
.enable_dev = mainboard_enable,
|
||||||
|
};
|
||||||
|
|
@ -0,0 +1,47 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2015 Google Inc.
|
||||||
|
* Copyright (C) 2015 Intel Corporation
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <stdint.h>
|
||||||
|
#include <string.h>
|
||||||
|
#include <soc/pei_data.h>
|
||||||
|
#include <soc/pei_wrapper.h>
|
||||||
|
|
||||||
|
void mainboard_fill_pei_data(struct pei_data *pei_data)
|
||||||
|
{
|
||||||
|
/* DQ byte map */
|
||||||
|
const u8 dq_map[2][12] = {
|
||||||
|
{ 0x0F, 0xF0, 0x00, 0xF0, 0x0F, 0xF0,
|
||||||
|
0x0F, 0x00, 0xFF, 0x00, 0xFF, 0x00 },
|
||||||
|
{ 0x33, 0xCC, 0x00, 0xCC, 0x33, 0xCC,
|
||||||
|
0x33, 0x00, 0xFF, 0x00, 0xFF, 0x00 } };
|
||||||
|
/* DQS CPU<>DRAM map */
|
||||||
|
const u8 dqs_map[2][8] = {
|
||||||
|
{ 0, 3, 1, 2, 4, 5, 6, 7 },
|
||||||
|
{ 1, 0, 4, 5, 2, 3, 6, 7 } };
|
||||||
|
|
||||||
|
/* Rcomp resistor */
|
||||||
|
const u16 RcompResistor[3] = { 200, 81, 162 };
|
||||||
|
|
||||||
|
/* Rcomp target */
|
||||||
|
const u16 RcompTarget[5] = { 100, 40, 40, 23, 40 };
|
||||||
|
|
||||||
|
memcpy(pei_data->dq_map, dq_map, sizeof(dq_map));
|
||||||
|
memcpy(pei_data->dqs_map, dqs_map, sizeof(dqs_map));
|
||||||
|
memcpy(pei_data->RcompResistor, RcompResistor,
|
||||||
|
sizeof(RcompResistor));
|
||||||
|
memcpy(pei_data->RcompTarget, RcompTarget,
|
||||||
|
sizeof(RcompTarget));
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,25 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2015 Intel Corporation
|
||||||
|
* Copyright (C) 2015 Google Inc.
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <soc/ramstage.h>
|
||||||
|
#include "gpio.h"
|
||||||
|
|
||||||
|
void mainboard_silicon_init_params(SILICON_INIT_UPD *params)
|
||||||
|
{
|
||||||
|
/* Configure pads prior to SiliconInit() in case there's any
|
||||||
|
* dependencies during hardware initialization. */
|
||||||
|
gpio_configure_pads(gpio_table, ARRAY_SIZE(gpio_table));
|
||||||
|
}
|
||||||
|
|
@ -0,0 +1,30 @@
|
||||||
|
/*
|
||||||
|
* This file is part of the coreboot project.
|
||||||
|
*
|
||||||
|
* Copyright (C) 2007-2010 coresystems GmbH
|
||||||
|
* Copyright (C) 2015 Google Inc.
|
||||||
|
* Copyright (C) 2015 Intel Corporation
|
||||||
|
*
|
||||||
|
* This program is free software; you can redistribute it and/or modify
|
||||||
|
* it under the terms of the GNU General Public License as published by
|
||||||
|
* the Free Software Foundation; version 2 of the License.
|
||||||
|
*
|
||||||
|
* This program is distributed in the hope that it will be useful,
|
||||||
|
* but WITHOUT ANY WARRANTY; without even the implied warranty of
|
||||||
|
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
|
||||||
|
* GNU General Public License for more details.
|
||||||
|
*/
|
||||||
|
|
||||||
|
#include <string.h>
|
||||||
|
#include <arch/acpi.h>
|
||||||
|
#include <soc/pei_data.h>
|
||||||
|
#include <soc/pei_wrapper.h>
|
||||||
|
#include <soc/romstage.h>
|
||||||
|
|
||||||
|
void mainboard_romstage_entry(struct romstage_params *params)
|
||||||
|
{
|
||||||
|
/* Fill out PEI DATA */
|
||||||
|
mainboard_fill_pei_data(params->pei_data);
|
||||||
|
/* Initliaze memory */
|
||||||
|
romstage_common(params);
|
||||||
|
}
|
||||||
Loading…
Reference in New Issue