Inteltool: Add i830/Tolapai/Ich4 support
Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5142 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
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@ -1,7 +1,7 @@
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -97,6 +97,67 @@ int print_intel_core_msrs(void)
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char *name;
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} msr_entry_t;
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static const msr_entry_t model6bx_global_msrs[] = {
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{ 0x0010, "IA32_TIME_STAMP_COUNTER" },
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{ 0x0017, "IA32_PLATFORM_ID" },
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{ 0x001b, "IA32_APIC_BASE" },
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{ 0x002a, "EBL_CR_POWERON" },
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{ 0x0033, "TEST_CTL" },
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{ 0x003f, "THERM_DIODE_OFFSET" },
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//{ 0x0079, "IA32_BIOS_UPDT_TRIG" }, // Seems to be RO
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{ 0x008b, "IA32_BIOS_SIGN_ID" },
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{ 0x00c1, "PERFCTR0" },
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{ 0x00c2, "PERFCTR1" },
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{ 0x011e, "BBL_CR_CTL3" },
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{ 0x0179, "IA32_MCG_CAP" },
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{ 0x017a, "IA32_MCG_STATUS" },
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{ 0x0198, "IA32_PERF_STATUS" },
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{ 0x0199, "IA32_PERF_CONTROL" },
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{ 0x019a, "IA32_CLOCK_MODULATION" },
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{ 0x01a0, "IA32_MISC_ENABLES" },
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{ 0x01d9, "IA32_DEBUGCTL" },
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{ 0x0200, "IA32_MTRR_PHYSBASE0" },
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{ 0x0201, "IA32_MTRR_PHYSMASK0" },
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{ 0x0202, "IA32_MTRR_PHYSBASE1" },
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{ 0x0203, "IA32_MTRR_PHYSMASK1" },
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{ 0x0204, "IA32_MTRR_PHYSBASE2" },
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{ 0x0205, "IA32_MTRR_PHYSMASK2" },
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{ 0x0206, "IA32_MTRR_PHYSBASE3" },
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{ 0x0207, "IA32_MTRR_PHYSMASK3" },
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{ 0x0208, "IA32_MTRR_PHYSBASE4" },
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{ 0x0209, "IA32_MTRR_PHYSMASK4" },
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{ 0x020a, "IA32_MTRR_PHYSBASE5" },
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{ 0x020b, "IA32_MTRR_PHYSMASK5" },
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{ 0x020c, "IA32_MTRR_PHYSBASE6" },
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{ 0x020d, "IA32_MTRR_PHYSMASK6" },
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{ 0x020e, "IA32_MTRR_PHYSBASE7" },
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{ 0x020f, "IA32_MTRR_PHYSMASK7" },
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{ 0x0250, "IA32_MTRR_FIX64K_00000" },
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{ 0x0258, "IA32_MTRR_FIX16K_80000" },
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{ 0x0259, "IA32_MTRR_FIX16K_A0000" },
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{ 0x0268, "IA32_MTRR_FIX4K_C0000" },
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{ 0x0269, "IA32_MTRR_FIX4K_C8000" },
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{ 0x026a, "IA32_MTRR_FIX4K_D0000" },
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{ 0x026b, "IA32_MTRR_FIX4K_D8000" },
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{ 0x026c, "IA32_MTRR_FIX4K_E0000" },
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{ 0x026d, "IA32_MTRR_FIX4K_E8000" },
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{ 0x026e, "IA32_MTRR_FIX4K_F0000" },
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{ 0x026f, "IA32_MTRR_FIX4K_F8000" },
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{ 0x02ff, "IA32_MTRR_DEF_TYPE" },
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{ 0x0400, "IA32_MC0_CTL" },
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{ 0x0401, "IA32_MC0_STATUS" },
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{ 0x0402, "IA32_MC0_ADDR" },
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//{ 0x0403, "IA32_MC0_MISC" }, // Seems to be RO
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{ 0x040c, "IA32_MC4_CTL" },
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{ 0x040d, "IA32_MC4_STATUS" },
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{ 0x040e, "IA32_MC4_ADDR" },
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//{ 0x040f, "IA32_MC4_MISC" } // Seems to be RO
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};
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static const msr_entry_t model6bx_per_core_msrs[] = {
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// single core only
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};
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static const msr_entry_t model6ex_global_msrs[] = {
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{ 0x0017, "IA32_PLATFORM_ID" },
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{ 0x002a, "EBL_CR_POWERON" },
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@ -259,6 +320,7 @@ int print_intel_core_msrs(void)
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} cpu_t;
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cpu_t cpulist[] = {
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{ 0x006b0, model6bx_global_msrs, ARRAY_SIZE(model6bx_global_msrs), NULL, 0 },
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{ 0x006e0, model6ex_global_msrs, ARRAY_SIZE(model6ex_global_msrs), model6ex_per_core_msrs, ARRAY_SIZE(model6ex_per_core_msrs) },
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{ 0x006f0, model6fx_global_msrs, ARRAY_SIZE(model6fx_global_msrs), model6fx_per_core_msrs, ARRAY_SIZE(model6fx_per_core_msrs) },
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};
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@ -315,7 +377,8 @@ int print_intel_core_msrs(void)
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if (fd_msr < 0)
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break;
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#endif
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printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
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if (cpu->num_per_core_msrs)
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printf("\n====================== UNIQUE MSRs (core %d) ======================\n", core);
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for (i = 0; i < cpu->num_per_core_msrs; i++) {
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msr = rdmsr(cpu->per_core_msrs[i].number);
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@ -1,7 +1,7 @@
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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* Copyright (C) 2008-2010 by coresystems GmbH
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* written by Stefan Reinauer <stepan@coresystems.de>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -34,6 +34,7 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
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@ -1,7 +1,7 @@
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -47,6 +47,7 @@
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82830M 0x3575
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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@ -1,7 +1,7 @@
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -50,6 +50,7 @@ int print_mchbar(struct pci_dev *nb)
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case PCI_DEVICE_ID_INTEL_82443BX:
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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printf("This northbrigde does not have MCHBAR.\n");
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return 1;
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default:
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@ -1,7 +1,7 @@
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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* Copyright (C) 2008-2010 by coresystems GmbH
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License as published by
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@ -47,6 +47,7 @@ int print_epbar(struct pci_dev *nb)
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break;
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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printf("This northbrigde does not have EPBAR.\n");
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return 1;
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default:
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@ -97,6 +98,7 @@ int print_dmibar(struct pci_dev *nb)
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break;
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case PCI_DEVICE_ID_INTEL_82810:
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case PCI_DEVICE_ID_INTEL_82810DC:
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case PCI_DEVICE_ID_INTEL_82830M:
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printf("This northbrigde does not have DMIBAR.\n");
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return 1;
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default:
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@ -1,7 +1,7 @@
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/*
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* inteltool - dump all registers on an Intel CPU + chipset based system.
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*
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* Copyright (C) 2008 by coresystems GmbH
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* Copyright (C) 2008-2010 by coresystems GmbH
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* written by Stefan Reinauer <stepan@coresystems.de>
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*
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* This program is free software; you can redistribute it and/or modify
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@ -145,6 +145,68 @@ static const io_register_t ich8_pm_registers[] = {
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{ 0x7c, 4, "RESERVED" },
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};
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static const io_register_t ich4_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" },
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{ 0x02, 2, "PM1_EN" },
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{ 0x04, 4, "PM1_CNT" },
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{ 0x08, 4, "PM1_TMR" },
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{ 0x0c, 4, "RESERVED" },
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{ 0x10, 4, "PROC_CNT" },
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#if DANGEROUS_REGISTERS
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/* These registers return 0 on read, but reading them may cause
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* the system to enter C2/C3/C4 state, which might hang the system.
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*/
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{ 0x14, 1, "LV2 (Mobile)" },
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{ 0x15, 1, "LV3 (Mobile)" },
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{ 0x16, 1, "LV4 (Mobile)" },
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#endif
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{ 0x17, 1, "RESERVED" },
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{ 0x18, 4, "RESERVED" },
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{ 0x1c, 4, "RESERVED" },
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{ 0x20, 1, "PM2_CNT (Mobile)" },
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{ 0x21, 1, "RESERVED" },
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{ 0x22, 2, "RESERVED" },
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{ 0x24, 4, "RESERVED" },
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{ 0x28, 4, "GPE0_STS" },
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{ 0x2C, 4, "GPE0_EN" },
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{ 0x30, 4, "SMI_EN" },
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{ 0x34, 4, "SMI_STS" },
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{ 0x38, 2, "ALT_GP_SMI_EN" },
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{ 0x3a, 2, "ALT_GP_SMI_STS" },
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{ 0x3c, 4, "RESERVED" },
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{ 0x40, 2, "MON_SMI" },
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{ 0x42, 2, "RESERVED" },
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{ 0x44, 2, "DEVACT_STS" },
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{ 0x46, 2, "RESERVED" },
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{ 0x48, 4, "DEVTRAP_EN" },
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{ 0x4c, 2, "BUS_ADDR_TRACK" },
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{ 0x4e, 2, "BUS_CYC_TRACK" },
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{ 0x50, 1, "SS_CNT (Mobile/Ultra Mobile)" },
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{ 0x51, 1, "RESERVED" },
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{ 0x52, 2, "RESERVED" },
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{ 0x54, 4, "RESERVED" },
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{ 0x58, 4, "RESERVED" },
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{ 0x5c, 4, "RESERVED" },
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/* Here start the TCO registers */
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{ 0x60, 1, "TCO_RLD" },
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{ 0x61, 1, "TCO_TMR" },
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{ 0x62, 1, "TCO_DAT_IN" },
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{ 0x63, 1, "TCO_DAT_OUT" },
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{ 0x64, 2, "TCO1_STS" },
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{ 0x66, 2, "TCO2_STS" },
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{ 0x68, 2, "TCO1_CNT" },
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{ 0x6a, 2, "TCO2_CNT" },
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{ 0x6c, 2, "TCO_MESSAGE" },
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{ 0x6e, 1, "TCO_WDSTATUS" },
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{ 0x6f, 1, "RESERVED" },
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{ 0x70, 1, "SW_IRQ_GEN" },
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{ 0x71, 1, "RESERVED" },
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{ 0x72, 2, "RESERVED" },
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{ 0x74, 4, "RESERVED" },
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{ 0x78, 4, "RESERVED" },
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{ 0x7c, 4, "RESERVED" },
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};
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static const io_register_t ich0_pm_registers[] = {
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{ 0x00, 2, "PM1_STS" },
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{ 0x02, 2, "PM1_EN" },
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@ -269,6 +331,11 @@ int print_pmbase(struct pci_dev *sb)
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pm_registers = ich8_pm_registers;
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size = ARRAY_SIZE(ich8_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH4:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = ich4_pm_registers;
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size = ARRAY_SIZE(ich4_pm_registers);
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break;
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case PCI_DEVICE_ID_INTEL_ICH0:
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pmbase = pci_read_word(sb, 0x40) & 0xfffc;
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pm_registers = ich0_pm_registers;
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