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mb/google/guybrush: Initialize WWAN GPIOs the same for PCI vs USB 

Since the PCIE training for the USB WWAN card is no longer being run,
we can initialize the GPIOs the same for all WWAN cards.

BUG=b:193036827
TEST=Boot and reboot with fibocom FM350-GL & L850GL modules

Signed-off-by: Martin Roth <martinroth@chromium.org>
Change-Id: Idc9a7cb883fc8dd6bbc6077b8ea99182f17f888b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/57317
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Martin Roth 2021-08-31 17:28:03 -06:00 committed by Felix Held
parent 76643f0dfb
commit 049e994fa8
2 changed files with 24 additions and 44 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

21
src/mainboard/google/guybrush/variants/baseboard/gpio.c
View File

@ -193,6 +193,12 @@ static const struct soc_amd_gpio early_gpio_table[] = {
/* EN_PWR_WWAN_X */ /* EN_PWR_WWAN_X */
PAD_GPO(GPIO_8, HIGH), PAD_GPO(GPIO_8, HIGH),
/* Put WWAN into reset */
/* WWAN_RST_L */
PAD_GPO(GPIO_24, LOW),
/* WWAN_DISABLE */
PAD_GPO(GPIO_85, HIGH),
/* Enable ESPI, GSC Interrupt & I2C Communication */ /* Enable ESPI, GSC Interrupt & I2C Communication */
/* GSC_SOC_INT_L */ /* GSC_SOC_INT_L */
PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY), PAD_INT(GPIO_3, PULL_NONE, EDGE_LOW, STATUS_DELIVERY),
@ -246,13 +252,13 @@ static const struct soc_amd_gpio early_gpio_table[] = {
*/ */
static const struct soc_amd_gpio bootblock_gpio_table[] = { static const struct soc_amd_gpio bootblock_gpio_table[] = {
/* Enable WWAN & WLAN power, Deassert WWAN reset */ /* Enable WWAN, Deassert WWAN reset, keep WWAN PCIe Aux reset asserted */
/* EN_PWR_WWAN_X */
PAD_GPO(GPIO_8, HIGH),
/* WWAN_RST_L */ /* WWAN_RST_L */
PAD_GPO(GPIO_24, HIGH), PAD_GPO(GPIO_24, HIGH),
/* WWAN_DISABLE */ /* WWAN_DISABLE */
PAD_GPO(GPIO_85, LOW), PAD_GPO(GPIO_85, LOW),
/* Enable WLAN */
/* WLAN_DISABLE */ /* WLAN_DISABLE */
PAD_GPO(GPIO_130, LOW), PAD_GPO(GPIO_130, LOW),
}; };
@ -264,14 +270,6 @@ static const struct soc_amd_gpio sleep_gpio_table[] = {
/* PCIE_RST needs to be brought high before FSP-M runs */ /* PCIE_RST needs to be brought high before FSP-M runs */
static const struct soc_amd_gpio pcie_gpio_table[] = { static const struct soc_amd_gpio pcie_gpio_table[] = {
/* Allow WWAN power to be overridden by platform */
/* EN_PWR_WWAN_X */
PAD_GPO(GPIO_8, HIGH),
/* WWAN_RST_L */
PAD_GPO(GPIO_24, HIGH),
/* WWAN_DISABLE */
PAD_GPO(GPIO_85, LOW),
/* Deassert all AUX_RESET lines & PCIE_RST */ /* Deassert all AUX_RESET lines & PCIE_RST */
/* WWAN_AUX_RESET_L */ /* WWAN_AUX_RESET_L */
PAD_GPO(GPIO_18, HIGH), PAD_GPO(GPIO_18, HIGH),
@ -319,6 +317,7 @@ const struct soc_amd_gpio *__weak variant_override_gpio_table(size_t *size)
const struct soc_amd_gpio * __weak variant_early_override_gpio_table(size_t *size) const struct soc_amd_gpio * __weak variant_early_override_gpio_table(size_t *size)
{ {
/* Note that when overriding this, board ID & CBI is not available */
*size = 0; *size = 0;
return NULL; return NULL;
} }

47
src/mainboard/google/guybrush/variants/guybrush/gpio.c
View File

@ -8,7 +8,7 @@
#include <baseboard/variants.h> #include <baseboard/variants.h>
/* This table is used by guybrush variant with board version < 2. */ /* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid1_gpio_table[] = { static const struct soc_amd_gpio bid1_ramstage_gpio_table[] = {
/* Unused TP183 */ /* Unused TP183 */
PAD_NC(GPIO_31), PAD_NC(GPIO_31),
/* EN_SPKR */ /* EN_SPKR */
@ -21,41 +21,25 @@ static const struct soc_amd_gpio bid1_gpio_table[] = {
/* This table is used by guybrush variant with board version < 2. */ /* This table is used by guybrush variant with board version < 2. */
/* Use AUX Reset lines instead of PCIE_RST for Board Version 1 */ /* Use AUX Reset lines instead of PCIE_RST for Board Version 1 */
static const struct soc_amd_gpio bid1_early_gpio_table[] = { static const struct soc_amd_gpio override_early_gpio_table[] = {
/* SD_AUX_RESET_L */ /* SD_AUX_RESET_L */
PAD_GPO(GPIO_70, LOW), PAD_GPO(GPIO_70, LOW),
}; };
/* This table is used by guybrush variant with board version < 2. */ /* This table is used by guybrush variant with board version < 2. */
static const struct soc_amd_gpio bid1_pcie_gpio_table[] = { static const struct soc_amd_gpio bid1_pcie_gpio_table[] = {
/* EN_PWR_WWAN_X */
PAD_GPO(GPIO_8, LOW),
/* WWAN_RST_L */
PAD_GPO(GPIO_24, LOW),
/* WWAN_DISABLE */
PAD_GPO(GPIO_85, HIGH),
/* SD_AUX_RESET_L */ /* SD_AUX_RESET_L */
PAD_GPO(GPIO_70, HIGH), PAD_GPO(GPIO_70, HIGH),
}; };
/* This table is used by guybrush variant with board version >= 2. */
static const struct soc_amd_gpio bid2_pcie_gpio_table[] = {
/* EN_PWR_WWAN_X */
PAD_GPO(GPIO_8, LOW),
/* WWAN_RST_L */
PAD_GPO(GPIO_24, LOW),
/* WWAN_DISABLE */
PAD_GPO(GPIO_85, HIGH),
};
const struct soc_amd_gpio *variant_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
{ {
uint32_t board_version = board_id(); uint32_t board_version = board_id();
*size = 0; *size = 0;
if (board_version < 2) { if (board_version < 2) {
*size = ARRAY_SIZE(bid1_gpio_table); *size = ARRAY_SIZE(bid1_ramstage_gpio_table);
return bid1_gpio_table; return bid1_ramstage_gpio_table;
} }
return NULL; return NULL;
@ -63,27 +47,24 @@ const struct soc_amd_gpio *variant_override_gpio_table(size_t *size)
const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_early_override_gpio_table(size_t *size)
{ {
uint32_t board_version = board_id(); /*
*size = 0; * This code is run before the EC is available to check the board ID
* since this is needed to work on Board ID 1 and is unused on other
if (board_version < 2) { * versions of guybrush, just enable it.
*size = ARRAY_SIZE(bid1_early_gpio_table); *
return bid1_early_gpio_table; * Guybrush BID>1: Unused TP27; BID==1: SD_AUX_RESET_L
} */
*size = ARRAY_SIZE(override_early_gpio_table);
return NULL; return override_early_gpio_table;
} }
const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size) const struct soc_amd_gpio *variant_pcie_override_gpio_table(size_t *size)
{ {
uint32_t board_version = board_id(); uint32_t board_version = board_id();
*size = 0; *size = 0;
if (board_version < 2) { if (board_version < 2) {
*size = ARRAY_SIZE(bid1_pcie_gpio_table); *size = ARRAY_SIZE(bid1_pcie_gpio_table);
return bid1_pcie_gpio_table; return bid1_pcie_gpio_table;
} }
return NULL;
*size = ARRAY_SIZE(bid2_pcie_gpio_table);
return bid2_pcie_gpio_table;
} }