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sb,soc/intel: Set IOAPIC redirection entry count 

The number of redirection table entries (aka interrupt vectors) inside
an I/O APIC may depend of the SKU, with the related register being of
type read/write-once. Provide support utilities to either lock or set
this registers value.

Change-Id: I8da869ba390dd821b43032e4ccbc9291c39e6bab
Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/55289
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
This commit is contained in:
Kyösti Mälkki 2021-06-06 08:04:28 +03:00 committed by Felix Held
parent e8601f4777
commit 04a40379b0
10 changed files with 61 additions and 73 deletions
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5
src/arch/x86/include/arch/ioapic.h
View File

@ -31,6 +31,11 @@ void io_apic_write(void *ioapic_base, u32 reg, u32 value);
void set_ioapic_id(void *ioapic_base, u8 ioapic_id);
u8 get_ioapic_id(void *ioapic_base);
u8 get_ioapic_version(void *ioapic_base);
unsigned int ioapic_get_max_vectors(void *ioapic_base);
void ioapic_set_max_vectors(void *ioapic_base, int mre_count);
void ioapic_lock_max_vectors(void *ioapic_base);
void setup_ioapic(void *ioapic_base, u8 ioapic_id);
void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb);

48
src/arch/x86/ioapic.c
View File

@ -27,18 +27,44 @@ static void write_vector(void *ioapic_base, u8 vector, u32 high, u32 low)
vector, high, low);
}
static int ioapic_interrupt_count(void *ioapic_base)
/* Bits 23-16 of register 0x01 specify the maximum redirection entry, which
* is the number of interrupts minus 1. */
unsigned int ioapic_get_max_vectors(void *ioapic_base)
{
/* Read the available number of interrupts. */
int ioapic_interrupts = (io_apic_read(ioapic_base, 0x01) >> 16) & 0xff;
if (!ioapic_interrupts || ioapic_interrupts == 0xff)
ioapic_interrupts = 23;
ioapic_interrupts += 1; /* Bits 23-16 specify the maximum redirection
entry, which is the number of interrupts
minus 1. */
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", ioapic_interrupts);
u32 reg;
u8 count;
return ioapic_interrupts;
reg = io_apic_read(ioapic_base, 0x01);
count = reg >> 16;
if (!count || count == 0xff)
count = 23;
count++;
printk(BIOS_DEBUG, "IOAPIC: %d interrupts\n", count);
return count;
}
/* Set maximum number of redirection entries (MRE). It is write-once register
* for some chipsets, and a negative mre_count will lock it to the number
* of vectors read from the register. */
void ioapic_set_max_vectors(void *ioapic_base, int mre_count)
{
u32 reg;
u8 count;
reg = io_apic_read(ioapic_base, 0x01);
count = reg >> 16;
if (mre_count > 0)
count = mre_count - 1;
reg &= ~(0xff << 16);
reg |= count << 16;
io_apic_write(ioapic_base, 0x01, count);
}
void ioapic_lock_max_vectors(void *ioapic_base)
{
ioapic_set_max_vectors(ioapic_base, -1);
}
static void clear_vectors(void *ioapic_base, u8 first, u8 last)
@ -134,6 +160,6 @@ void ioapic_set_boot_config(void *ioapic_base, bool irq_on_fsb)
void setup_ioapic(void *ioapic_base, u8 ioapic_id)
{
set_ioapic_id(ioapic_base, ioapic_id);
clear_vectors(ioapic_base, 0, ioapic_interrupt_count(ioapic_base) - 1);
clear_vectors(ioapic_base, 0, ioapic_get_max_vectors(ioapic_base) - 1);
route_i8259_irq0(ioapic_base);
}

11
src/soc/intel/broadwell/pch/lpc.c
View File

@ -25,8 +25,6 @@
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
/* Assign unique bus/dev/fn for I/O APIC */
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
@ -34,13 +32,8 @@ static void pch_enable_ioapic(struct device *dev)
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/* PCH-LP has 40 redirection entries */
ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
}
static void enable_hpet(struct device *dev)

14
src/soc/intel/common/block/lpc/lpc_lib.c
View File

@ -274,22 +274,16 @@ void lpc_disable_clkrun(void)
pci_write_config8(PCH_DEV_LPC, LPC_PCCTL, pcctl & ~LPC_PCCTL_CLKRUN_EN);
}
/* PCH I/O APIC redirection entries */
#define PCH_REDIR_ETR 120
/* Enable PCH IOAPIC */
void pch_enable_ioapic(void)
{
uint32_t reg32;
/* PCH-LP has 120 redirection entries */
const int redir_entries = 120;
set_ioapic_id((void *)IO_APIC_ADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (redir_entries - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
}
static const uint8_t pch_interrupt_routing[PIRQ_COUNT] = {

13
src/soc/intel/denverton_ns/lpc.c
View File

@ -21,8 +21,8 @@
#include "chip.h"
/* PCH-LP redirection entries */
#define PCH_LP_REDIR_ETR 120
/* PCH I/O APIC redirection entries */
#define PCH_REDIR_ETR 120
/**
* Set miscellaneous static southbridge features.
@ -31,17 +31,10 @@
*/
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
set_ioapic_id((void *)IO_APIC_ADDR, IO_APIC0);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read((void *)IO_APIC_ADDR, 0x01);
reg32 &= ~0x00ff0000;
reg32 |= (PCH_LP_REDIR_ETR - 1) << 16;
io_apic_write((void *)IO_APIC_ADDR, 0x01, reg32);
ioapic_set_max_vectors(VIO_APIC_VADDR, PCH_REDIR_ETR);
}
/* interrupt router lookup for internal devices */

5
src/southbridge/intel/bd82x6x/lpc.c
View File

@ -37,8 +37,6 @@ typedef struct southbridge_intel_bd82x6x_config config_t;
*/
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
/* Assign unique bus/dev/fn for I/O APIC */
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
@ -46,8 +44,7 @@ static void pch_enable_ioapic(struct device *dev)
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
ioapic_lock_max_vectors(VIO_APIC_VADDR);
}
static void pch_enable_serial_irqs(struct device *dev)

9
src/southbridge/intel/i82801ix/lpc.c
View File

@ -27,20 +27,13 @@ typedef struct southbridge_intel_i82801ix_config config_t;
static void i82801ix_enable_apic(struct device *dev)
{
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable IOAPIC. Keep APIC Range Select at zero. */
RCBA8(0x31ff) = 0x03;
/* We have to read 0x31ff back if bit0 changed. */
RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */
*ioapic_index = 0x01;
reg32 = *ioapic_data;
*ioapic_index = 0x01;
*ioapic_data = reg32;
ioapic_lock_max_vectors(VIO_APIC_VADDR);
setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
}

9
src/southbridge/intel/i82801jx/lpc.c
View File

@ -28,20 +28,13 @@ typedef struct southbridge_intel_i82801jx_config config_t;
static void i82801jx_enable_apic(struct device *dev)
{
u32 reg32;
volatile u32 *ioapic_index = (volatile u32 *)(IO_APIC_ADDR);
volatile u32 *ioapic_data = (volatile u32 *)(IO_APIC_ADDR + 0x10);
/* Enable IOAPIC. Keep APIC Range Select at zero. */
RCBA8(0x31ff) = 0x03;
/* We have to read 0x31ff back if bit0 changed. */
RCBA8(0x31ff);
/* Lock maximum redirection entries (MRE), R/WO register. */
*ioapic_index = 0x01;
reg32 = *ioapic_data;
*ioapic_index = 0x01;
*ioapic_data = reg32;
ioapic_lock_max_vectors(VIO_APIC_VADDR);
setup_ioapic(VIO_APIC_VADDR, 2); /* ICH7 code uses id 2. */
}

6
src/southbridge/intel/ibexpeak/lpc.c
View File

@ -34,12 +34,10 @@ typedef struct southbridge_intel_ibexpeak_config config_t;
*/
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
set_ioapic_id(VIO_APIC_VADDR, 0x01);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
ioapic_lock_max_vectors(VIO_APIC_VADDR);
}
static void pch_enable_serial_irqs(struct device *dev)

14
src/southbridge/intel/lynxpoint/lpc.c
View File

@ -31,8 +31,6 @@
*/
static void pch_enable_ioapic(struct device *dev)
{
u32 reg32;
/* Assign unique bus/dev/fn for I/O APIC */
pci_write_config16(dev, LPC_IBDF,
PCH_IOAPIC_PCI_BUS << 8 | PCH_IOAPIC_PCI_SLOT << 3);
@ -40,13 +38,11 @@ static void pch_enable_ioapic(struct device *dev)
set_ioapic_id(VIO_APIC_VADDR, 0x02);
/* affirm full set of redirection table entries ("write once") */
reg32 = io_apic_read(VIO_APIC_VADDR, 0x01);
if (pch_is_lp()) {
/* PCH-LP has 39 redirection entries */
reg32 &= ~0x00ff0000;
reg32 |= 0x00270000;
}
io_apic_write(VIO_APIC_VADDR, 0x01, reg32);
/* PCH-LP has 40 redirection entries */
if (pch_is_lp())
ioapic_set_max_vectors(VIO_APIC_VADDR, 40);
else
ioapic_lock_max_vectors(VIO_APIC_VADDR);
}
static void pch_enable_serial_irqs(struct device *dev)