AMD K8 fam10: Refactor logic around SB_HT_CHAIN_ON_BUS0
Change-Id: I452a93af452073eeac4e6cb9bbc232dc59e911c1 Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/8365 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <edward.ocallaghan@koparo.com> Reviewed-by: Timothy Pearson <tpearson@raptorengineeringinc.com>
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@ -216,20 +216,12 @@ static u32 amdfam10_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool
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* so we set the subordinate bus number to 0xff for the moment.
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*/
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if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) {
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if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink)
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max++;
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} else if (is_sblink) {
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} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) {
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max++;
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} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) {
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// We can have 16 segmment and every segment have 256 bus,
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// For that case need the kernel support mmio pci config.
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/* One node can have 8 link and segn is the same. */
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max++;
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/* One node can have 8 link and segn is the same. */
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if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink)
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max = ALIGN_UP(max, 8);
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}
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link->secondary = max;
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link->subordinate = link->secondary;
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@ -178,17 +178,13 @@ static u32 amdk8_scan_chain(device_t dev, u32 nodeid, struct bus *link, bool is_
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* We have no idea how many busses are behind this bridge yet,
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* so we set the subordinate bus number to 0xff for the moment.
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*/
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if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) {
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max++;
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} else if (is_sblink) {
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} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 == 1) {
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max++;
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} else if (CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) {
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/* Second chain will be on 0x40, third 0x80, forth 0xc0. */
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if ((CONFIG_SB_HT_CHAIN_ON_BUS0 == 0) || !is_sblink)
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max++;
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/* Second chain will be on 0x40, third 0x80, forth 0xc0. */
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if ((CONFIG_SB_HT_CHAIN_ON_BUS0 > 1) && !is_sblink)
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max = ALIGN_UP(max, 0x40);
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}
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link->secondary = max;
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link->subordinate = link->secondary;
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