inteltool: new definitions and cleanup
- Separate host bridges/DRAM controllers from LPC controllers in supported_chips_list[]. - Refine some names and macros. - Clean up some whitespace errors. - Add IDs and names of 5, 6 and 7 Series southbridges and the three latest Core CPU families with integrated memory controllers but do not implement any pretty printing routines for them yet. The first generation Core family is already supported, although it was wrongly named after the PCH and used the wrong ID. Also, the BAR values have been mangled to 32b instead of 64b. Both errors have been fixed and most basic support for the other two generations was added. Change-Id: Ief81e57f7c065cafac52e48b6364b57c72fcdf95 Signed-off-by: Stefan Tauner <stefan.tauner@gmx.at> Reviewed-on: http://review.coreboot.org/1574 Tested-by: build bot (Jenkins) Reviewed-by: Anton Kochkov <anton.kochkov@gmail.com>
This commit is contained in:
Stefan Tauner
Anton Kochkov
parent
9b48ef2733
commit
04c06005eb
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@ -30,36 +30,54 @@
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#include <unistd.h>
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#endif
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/*
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* http://pci-ids.ucw.cz/read/PC/8086
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* http://en.wikipedia.org/wiki/Intel_Tick-Tock
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* http://en.wikipedia.org/wiki/List_of_Intel_chipsets
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* http://en.wikipedia.org/wiki/Intel_Xeon_chipsets
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*/
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static const struct {
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uint16_t vendor_id, device_id;
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char *name;
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} supported_chips_list[] = {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "82443LX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "82443BX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "82443BX without AGP" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "i810" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810DC, "i810-DC100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_MC, "i810E DC-133" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "i830M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "i845" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "i865" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "82915G/P/GV/GL/PL/910GL" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "i945P" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "i945GM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "i945GSE" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PM965, "PM965" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_Q965, "Q963/965" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "i975X" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
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/* Host bridges/DRAM controllers (Northbridges) */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443LX, "443LX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX, "443BX" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82443BX_NO_AGP, "443BX without AGP" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810, "810" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810_DC, "810-DC100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82810E_DC, "810E DC-133" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82830M, "830M" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82845, "845" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82865, "865" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82915, "915G/P/GV/GL/PL/910GL" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945P, "945P" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GM, "945GM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82945GSE, "945GSE" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82965PM, "965PM" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q965, "Q963/82Q965" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82975X, "975X" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82G33, "P35/G33/G31/P31" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q33, "Q33" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X58, "X58" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_HM65E, "HM65 Express" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_GS45, "GS45ME" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82Q35, "Q35" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X38, "X38/X48" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X4X, "GL40/GS40/GM45/GS45/PM45" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82X58, "X58" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_DXXX, "Atom D400/500 Series" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ATOM_NXXX, "Atom N400 Series" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO, "SCH Poulsbo" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
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/* Host bridges /DRAM controllers integrated in CPUs */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_1ST_GEN, "1st generation (Westmere family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_2ND_GEN, "2nd generation (Sandy Bridge family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_3RD_GEN, "3rd generation (Ivy Bridge family) Core Processor" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_CORE_4TH_GEN, "4th generation (Haswell family) Core Processor" },
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/* Southbridges (LPC controllers) */
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "371AB/EB/MB" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH10R, "ICH10R" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DH, "ICH9DH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH9DO, "ICH9DO" },
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@ -81,14 +99,58 @@ static const struct {
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH0, "ICH0" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH, "ICH" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82371XX, "82371AB/EB/MB" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_X44, "82X38/X48" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_32X0, "3200/3210" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "Intel 63xx I/O Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000P, "Intel i5000P Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000X, "Intel i5000X Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000Z, "Intel i5000Z Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I5000V, "Intel i5000V Memory Controller Hub" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_I63XX, "631xESB/632xESB/3100" },
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{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC, "SCH Poulsbo" },
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{ PCI_VENDOR_ID_INTEL, 0x3b00, "3400 Desktop" },
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{ PCI_VENDOR_ID_INTEL, 0x3b01, "3400 Mobile" },
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{ PCI_VENDOR_ID_INTEL, 0x3b02, "P55" },
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{ PCI_VENDOR_ID_INTEL, 0x3b03, "PM55" },
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{ PCI_VENDOR_ID_INTEL, 0x3b06, "H55" },
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{ PCI_VENDOR_ID_INTEL, 0x3b07, "QM57" },
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{ PCI_VENDOR_ID_INTEL, 0x3b08, "H57" },
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{ PCI_VENDOR_ID_INTEL, 0x3b09, "HM55" },
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{ PCI_VENDOR_ID_INTEL, 0x3b0a, "Q57" },
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{ PCI_VENDOR_ID_INTEL, 0x3b0b, "HM57" },
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{ PCI_VENDOR_ID_INTEL, 0x3b0d, "3400 Mobile SFF" },
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{ PCI_VENDOR_ID_INTEL, 0x3b0e, "B55" },
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{ PCI_VENDOR_ID_INTEL, 0x3b0f, "QS57" },
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{ PCI_VENDOR_ID_INTEL, 0x3b12, "3400" },
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{ PCI_VENDOR_ID_INTEL, 0x3b14, "3420" },
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{ PCI_VENDOR_ID_INTEL, 0x3b16, "3450" },
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{ PCI_VENDOR_ID_INTEL, 0x3b1e, "B55" },
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{ PCI_VENDOR_ID_INTEL, 0x1c44, "Z68" },
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{ PCI_VENDOR_ID_INTEL, 0x1c46, "P67" },
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{ PCI_VENDOR_ID_INTEL, 0x1c47, "UM67" },
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{ PCI_VENDOR_ID_INTEL, 0x1c49, "HM65" },
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{ PCI_VENDOR_ID_INTEL, 0x1c4a, "H67" },
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{ PCI_VENDOR_ID_INTEL, 0x1c4b, "HM67" },
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{ PCI_VENDOR_ID_INTEL, 0x1c4c, "Q65" },
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{ PCI_VENDOR_ID_INTEL, 0x1c4d, "QS67" },
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{ PCI_VENDOR_ID_INTEL, 0x1c4e, "Q67" },
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{ PCI_VENDOR_ID_INTEL, 0x1c4f, "QM67" },
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{ PCI_VENDOR_ID_INTEL, 0x1c50, "B65" },
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{ PCI_VENDOR_ID_INTEL, 0x1c52, "C202" },
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{ PCI_VENDOR_ID_INTEL, 0x1c54, "C204" },
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{ PCI_VENDOR_ID_INTEL, 0x1c56, "C206" },
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{ PCI_VENDOR_ID_INTEL, 0x1c5c, "H61" },
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{ PCI_VENDOR_ID_INTEL, 0x1d40, "X79" },
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{ PCI_VENDOR_ID_INTEL, 0x1d41, "X79" },
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{ PCI_VENDOR_ID_INTEL, 0x1e44, "Z77" },
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{ PCI_VENDOR_ID_INTEL, 0x1e46, "Z75" },
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{ PCI_VENDOR_ID_INTEL, 0x1e47, "Q77" },
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{ PCI_VENDOR_ID_INTEL, 0x1e48, "Q75" },
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{ PCI_VENDOR_ID_INTEL, 0x1e49, "B75" },
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{ PCI_VENDOR_ID_INTEL, 0x1e4a, "H77" },
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{ PCI_VENDOR_ID_INTEL, 0x1e53, "C216" },
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{ PCI_VENDOR_ID_INTEL, 0x1e55, "QM77" },
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{ PCI_VENDOR_ID_INTEL, 0x1e56, "QS77" },
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{ PCI_VENDOR_ID_INTEL, 0x1e57, "HM77" },
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{ PCI_VENDOR_ID_INTEL, 0x1e58, "UM77" },
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{ PCI_VENDOR_ID_INTEL, 0x1e59, "HM76" },
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{ PCI_VENDOR_ID_INTEL, 0x1e5d, "HM75" },
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{ PCI_VENDOR_ID_INTEL, 0x1e5e, "HM70" },
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{ PCI_VENDOR_ID_INTEL, 0x1e5f, "NM70" },
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{ PCI_VENDOR_ID_INTEL, 0x2310, "DH89xxCC" },
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};
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#ifndef __DARWIN__
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@ -309,7 +371,7 @@ int main(int argc, char *argv[])
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* left-shifted "Extended Model" fields.
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* http://download.intel.com/design/processor/applnots/24161832.pdf
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*/
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printf("Intel CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
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printf("CPU: Processor Type: %x, Family %x, Model %x, Stepping %x\n",
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(id >> 12) & 0x3, ((id >> 8) & 0xf) + ((id >> 20) & 0xff),
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((id >> 12) & 0xf0) + ((id >> 4) & 0xf), (id & 0xf));
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@ -321,10 +383,10 @@ int main(int argc, char *argv[])
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if (sb->device_id == supported_chips_list[i].device_id)
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sbname = supported_chips_list[i].name;
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printf("Intel Northbridge: %04x:%04x (%s)\n",
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printf("Northbridge: %04x:%04x (%s)\n",
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nb->vendor_id, nb->device_id, nbname);
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printf("Intel Southbridge: %04x:%04x (%s)\n",
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printf("Southbridge: %04x:%04x (%s)\n",
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sb->vendor_id, sb->device_id, sbname);
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/* Now do the deed */
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@ -63,27 +63,27 @@
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO_LPC 0x8119
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#define PCI_DEVICE_ID_INTEL_82810 0x7120
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#define PCI_DEVICE_ID_INTEL_82810DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82810E_MC 0x7124
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#define PCI_DEVICE_ID_INTEL_82810_DC 0x7122
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#define PCI_DEVICE_ID_INTEL_82810E_DC 0x7124
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#define PCI_DEVICE_ID_INTEL_82830M 0x3575
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#define PCI_DEVICE_ID_INTEL_82845 0x1a30
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#define PCI_DEVICE_ID_INTEL_82865 0x2570
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#define PCI_DEVICE_ID_INTEL_82915 0x2580
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#define PCI_DEVICE_ID_INTEL_82945P 0x2770
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#define PCI_DEVICE_ID_INTEL_82945GM 0x27a0
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#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
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#define PCI_DEVICE_ID_INTEL_PM965 0x2a00
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#define PCI_DEVICE_ID_INTEL_Q965 0x2990
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#define PCI_DEVICE_ID_INTEL_82945GSE 0x27ac
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#define PCI_DEVICE_ID_INTEL_82965PM 0x2a00
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#define PCI_DEVICE_ID_INTEL_82Q965 0x2990
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#define PCI_DEVICE_ID_INTEL_82975X 0x277c
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#define PCI_DEVICE_ID_INTEL_82Q35 0x29b0
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#define PCI_DEVICE_ID_INTEL_82G33 0x29c0
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#define PCI_DEVICE_ID_INTEL_82Q33 0x29d0
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#define PCI_DEVICE_ID_INTEL_X44 0x29e0
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#define PCI_DEVICE_ID_INTEL_82X38 0x29e0
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#define PCI_DEVICE_ID_INTEL_32X0 0x29f0
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#define PCI_DEVICE_ID_INTEL_GS45 0x2a40
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#define PCI_DEVICE_ID_INTEL_X58 0x3405
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
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#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
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#define PCI_DEVICE_ID_INTEL_82X4X 0x2a40
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#define PCI_DEVICE_ID_INTEL_82X58 0x3405
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#define PCI_DEVICE_ID_INTEL_SCH_POULSBO 0x8100
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#define PCI_DEVICE_ID_INTEL_ATOM_DXXX 0xa000
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#define PCI_DEVICE_ID_INTEL_I63XX 0x2670
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#define PCI_DEVICE_ID_INTEL_I5000X 0x25c0
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#define PCI_DEVICE_ID_INTEL_I5000P 0x25d8
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/* untested, but almost identical to D-series */
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#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
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#define PCI_DEVICE_ID_INTEL_ATOM_NXXX 0xa010
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#define PCI_DEVICE_ID_INTEL_82443LX 0x7180
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/* 82443BX has a different device ID if AGP is disabled (hardware-wise). */
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@ -102,7 +102,11 @@
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/* 82371AB/EB/MB use the same device ID value. */
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#define PCI_DEVICE_ID_INTEL_82371XX 0x7110
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#define PCI_DEVICE_ID_INTEL_HM65E 0x0104
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/* Intel starts counting these generations with the integration of the DRAM controller */
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#define PCI_DEVICE_ID_INTEL_CORE_1ST_GEN 0x0044 /* Westmere */
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#define PCI_DEVICE_ID_INTEL_CORE_2ND_GEN 0x0104 /* Sandy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_3RD_GEN 0x0154 /* Ivy Bridge */
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#define PCI_DEVICE_ID_INTEL_CORE_4TH_GEN 0x0c04 /* Haswell */
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#define ARRAY_SIZE(a) ((int)(sizeof(a) / sizeof((a)[0])))
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@ -108,20 +108,20 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
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case PCI_DEVICE_ID_INTEL_82945GM:
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case PCI_DEVICE_ID_INTEL_82945GSE:
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case PCI_DEVICE_ID_INTEL_82945P:
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case PCI_DEVICE_ID_INTEL_82975X:
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case PCI_DEVICE_ID_INTEL_82975X:
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mchbar_phys = pci_read_long(nb, 0x44) & 0xfffffffe;
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break;
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case PCI_DEVICE_ID_INTEL_PM965:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_Q965:
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case PCI_DEVICE_ID_INTEL_82965PM:
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case PCI_DEVICE_ID_INTEL_82Q35:
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case PCI_DEVICE_ID_INTEL_82G33:
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case PCI_DEVICE_ID_INTEL_82Q33:
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mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
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mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
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break;
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case PCI_DEVICE_ID_INTEL_82Q965:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
|
||||
mchbar_phys = pci_read_long(nb, 0x48);
|
||||
mchbar_phys = pci_read_long(nb, 0x48);
|
||||
|
||||
/* Test if bit 0 of the MCHBAR reg is 1 to enable memory reads.
|
||||
* If it isn't, try to set it. This may fail, because there is
|
||||
|
|
@ -131,36 +131,45 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
|
|||
|
||||
if(!(mchbar_phys & 1))
|
||||
{
|
||||
printf("Access to the MCHBAR is currently disabled, "\
|
||||
"attempting to enable.\n");
|
||||
printf("Access to the MCHBAR is currently disabled, "
|
||||
"attempting to enable.\n");
|
||||
mchbar_phys |= 0x1;
|
||||
pci_write_long(nb, 0x48, mchbar_phys);
|
||||
if(pci_read_long(nb, 0x48) & 1)
|
||||
if(pci_read_long(nb, 0x48) & 1)
|
||||
printf("Enabled successfully.\n");
|
||||
else
|
||||
printf("Enable FAILED!\n");
|
||||
}
|
||||
mchbar_phys &= 0xfffffffe;
|
||||
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
|
||||
break;
|
||||
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_82443LX:
|
||||
case PCI_DEVICE_ID_INTEL_82443BX:
|
||||
case PCI_DEVICE_ID_INTEL_82810:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_MC:
|
||||
case PCI_DEVICE_ID_INTEL_82810DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82830M:
|
||||
printf("This northbridge does not have MCHBAR.\n");
|
||||
return 1;
|
||||
case PCI_DEVICE_ID_INTEL_GS45:
|
||||
case PCI_DEVICE_ID_INTEL_X44:
|
||||
case PCI_DEVICE_ID_INTEL_82X4X:
|
||||
case PCI_DEVICE_ID_INTEL_82X38:
|
||||
case PCI_DEVICE_ID_INTEL_32X0:
|
||||
mchbar_phys = pci_read_long(nb, 0x48) & 0xfffffffe;
|
||||
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HM65E:
|
||||
mchbar_phys = pci_read_long(nb, 0x48) & 0xffff8000;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
|
||||
mchbar_phys = pci_read_long(nb, 0x48);
|
||||
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
|
||||
mchbar_phys &= 0x0000000fffffc000UL; /* 35:14 */
|
||||
mch_registers = NULL; /* No public documentation */
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
|
||||
mch_registers = sandybridge_mch_registers;
|
||||
size = ARRAY_SIZE(sandybridge_mch_registers);
|
||||
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
|
||||
mchbar_phys = pci_read_long(nb, 0x48);
|
||||
mchbar_phys |= ((uint64_t)pci_read_long(nb, 0x4c)) << 32;
|
||||
mchbar_phys &= 0x0000007fffff8000UL; /* 38:15 */
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping MCHBAR on this northbridge is not (yet) supported.\n");
|
||||
|
|
@ -183,28 +192,29 @@ int print_mchbar(struct pci_dev *nb, struct pci_access *pacc)
|
|||
printf("MCHBAR = 0x%08" PRIx64 " (MEM)\n\n", mchbar_phys);
|
||||
|
||||
if (mch_registers != NULL) {
|
||||
printf("%d registers:\n", size);
|
||||
for (i = 0; i < size; i++) {
|
||||
switch (mch_registers[i].size) {
|
||||
case 8:
|
||||
printf("mchbase+0x%04x: 0x%08lx (%s)\n",
|
||||
printf("mchbase+0x%04x: 0x%016lx (%s)\n",
|
||||
mch_registers[i].addr,
|
||||
*(uint64_t *)(mchbar+mch_registers[i].addr),
|
||||
mch_registers[i].name);
|
||||
break;
|
||||
case 4:
|
||||
printf("mchbase+0x%04x: 0x%08x (%s)\n",
|
||||
printf("mchbase+0x%04x: 0x%08x (%s)\n",
|
||||
mch_registers[i].addr,
|
||||
*(uint32_t *)(mchbar+mch_registers[i].addr),
|
||||
mch_registers[i].name);
|
||||
break;
|
||||
case 2:
|
||||
printf("mchbase+0x%04x: 0x%04x (%s)\n",
|
||||
printf("mchbase+0x%04x: 0x%04x (%s)\n",
|
||||
mch_registers[i].addr,
|
||||
*(uint16_t *)(mchbar+mch_registers[i].addr),
|
||||
mch_registers[i].name);
|
||||
break;
|
||||
case 1:
|
||||
printf("mchbase+0x%04x: 0x%02x (%s)\n",
|
||||
printf("mchbase+0x%04x: 0x%02x (%s)\n",
|
||||
mch_registers[i].addr,
|
||||
*(uint8_t *)(mchbar+mch_registers[i].addr),
|
||||
mch_registers[i].name);
|
||||
|
|
|
|||
|
|
@ -94,22 +94,22 @@ int print_epbar(struct pci_dev *nb)
|
|||
case PCI_DEVICE_ID_INTEL_82975X:
|
||||
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_PM965:
|
||||
case PCI_DEVICE_ID_INTEL_Q965:
|
||||
case PCI_DEVICE_ID_INTEL_82Q35:
|
||||
case PCI_DEVICE_ID_INTEL_82G33:
|
||||
case PCI_DEVICE_ID_INTEL_82Q33:
|
||||
case PCI_DEVICE_ID_INTEL_X44:
|
||||
case PCI_DEVICE_ID_INTEL_82965PM:
|
||||
case PCI_DEVICE_ID_INTEL_82Q965:
|
||||
case PCI_DEVICE_ID_INTEL_82Q35:
|
||||
case PCI_DEVICE_ID_INTEL_82G33:
|
||||
case PCI_DEVICE_ID_INTEL_82Q33:
|
||||
case PCI_DEVICE_ID_INTEL_82X38:
|
||||
case PCI_DEVICE_ID_INTEL_32X0:
|
||||
case PCI_DEVICE_ID_INTEL_GS45:
|
||||
case PCI_DEVICE_ID_INTEL_82X4X:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
|
||||
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
|
||||
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
|
||||
break;
|
||||
epbar_phys = pci_read_long(nb, 0x40) & 0xfffffffe;
|
||||
epbar_phys |= ((uint64_t)pci_read_long(nb, 0x44)) << 32;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_82810:
|
||||
case PCI_DEVICE_ID_INTEL_82810DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_MC:
|
||||
case PCI_DEVICE_ID_INTEL_82810_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82830M:
|
||||
case PCI_DEVICE_ID_INTEL_82865:
|
||||
printf("This northbridge does not have EPBAR.\n");
|
||||
|
|
@ -156,32 +156,41 @@ int print_dmibar(struct pci_dev *nb)
|
|||
case PCI_DEVICE_ID_INTEL_82975X:
|
||||
dmibar_phys = pci_read_long(nb, 0x4c) & 0xfffffffe;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_PM965:
|
||||
case PCI_DEVICE_ID_INTEL_Q965:
|
||||
case PCI_DEVICE_ID_INTEL_82965PM:
|
||||
case PCI_DEVICE_ID_INTEL_82Q965:
|
||||
case PCI_DEVICE_ID_INTEL_82Q35:
|
||||
case PCI_DEVICE_ID_INTEL_82G33:
|
||||
case PCI_DEVICE_ID_INTEL_82Q33:
|
||||
case PCI_DEVICE_ID_INTEL_X44:
|
||||
case PCI_DEVICE_ID_INTEL_82X38:
|
||||
case PCI_DEVICE_ID_INTEL_32X0:
|
||||
case PCI_DEVICE_ID_INTEL_GS45:
|
||||
case PCI_DEVICE_ID_INTEL_82X4X:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
|
||||
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffffffe;
|
||||
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_82810:
|
||||
case PCI_DEVICE_ID_INTEL_82810DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_MC:
|
||||
case PCI_DEVICE_ID_INTEL_82810_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82865:
|
||||
printf("This northbridge does not have DMIBAR.\n");
|
||||
return 1;
|
||||
case PCI_DEVICE_ID_INTEL_X58:
|
||||
case PCI_DEVICE_ID_INTEL_82X58:
|
||||
dmibar_phys = pci_read_long(nb, 0x50) & 0xfffff000;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_HM65E:
|
||||
dmibar_phys = pci_read_long(nb, 0x68) & 0xfffff000;
|
||||
case PCI_DEVICE_ID_INTEL_CORE_1ST_GEN:
|
||||
dmibar_phys = pci_read_long(nb, 0x68);
|
||||
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
|
||||
dmibar_phys &= 0x0000000ffffff000UL; /* 35:12 */
|
||||
dmi_registers = NULL; /* No public documentation */
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_CORE_2ND_GEN:
|
||||
dmi_registers = sandybridge_dmi_registers;
|
||||
size = ARRAY_SIZE(sandybridge_dmi_registers);
|
||||
case PCI_DEVICE_ID_INTEL_CORE_3RD_GEN: /* pretty printing not implemented yet */
|
||||
dmibar_phys = pci_read_long(nb, 0x68);
|
||||
dmibar_phys |= ((uint64_t)pci_read_long(nb, 0x6c)) << 32;
|
||||
dmibar_phys &= 0x0000007ffffff000UL; /* 38:12 */
|
||||
break;
|
||||
default:
|
||||
printf("Error: Dumping DMIBAR on this northbridge is not (yet) supported.\n");
|
||||
|
|
@ -251,22 +260,22 @@ int print_pciexbar(struct pci_dev *nb)
|
|||
case PCI_DEVICE_ID_INTEL_82975X:
|
||||
pciexbar_reg = pci_read_long(nb, 0x48);
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_PM965:
|
||||
case PCI_DEVICE_ID_INTEL_Q965:
|
||||
case PCI_DEVICE_ID_INTEL_82Q35:
|
||||
case PCI_DEVICE_ID_INTEL_82G33:
|
||||
case PCI_DEVICE_ID_INTEL_82Q33:
|
||||
case PCI_DEVICE_ID_INTEL_X44:
|
||||
case PCI_DEVICE_ID_INTEL_82965PM:
|
||||
case PCI_DEVICE_ID_INTEL_82Q965:
|
||||
case PCI_DEVICE_ID_INTEL_82Q35:
|
||||
case PCI_DEVICE_ID_INTEL_82G33:
|
||||
case PCI_DEVICE_ID_INTEL_82Q33:
|
||||
case PCI_DEVICE_ID_INTEL_82X38:
|
||||
case PCI_DEVICE_ID_INTEL_32X0:
|
||||
case PCI_DEVICE_ID_INTEL_GS45:
|
||||
case PCI_DEVICE_ID_INTEL_82X4X:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_DXXX:
|
||||
case PCI_DEVICE_ID_INTEL_ATOM_NXXX:
|
||||
pciexbar_reg = pci_read_long(nb, 0x60);
|
||||
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
|
||||
break;
|
||||
pciexbar_reg = pci_read_long(nb, 0x60);
|
||||
pciexbar_reg |= ((uint64_t)pci_read_long(nb, 0x64)) << 32;
|
||||
break;
|
||||
case PCI_DEVICE_ID_INTEL_82810:
|
||||
case PCI_DEVICE_ID_INTEL_82810DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_MC:
|
||||
case PCI_DEVICE_ID_INTEL_82810_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82810E_DC:
|
||||
case PCI_DEVICE_ID_INTEL_82865:
|
||||
printf("Error: This northbridge does not have PCIEXBAR.\n");
|
||||
return 1;
|
||||
|
|
|
|||
Loading…
Reference in New Issue