Move CAR settings for all GX1, GX2, LX and Intel Slot2 boards to the CPU.
This automatically adds the settings for those boards that didn't have settings at all yet. Also, small fixup to compareboard. Signed-off-by: Stefan Reinauer <stepan@coresystems.de> Acked-by: Stefan Reinauer <stepan@coresystems.de> --> Please help porting all boards from newconfig to Kconfig <-- This is a lot of janitor work and we can use your helping hands. The sooner we can get rid of Kbuild, the better. The KBuild report on the mailing list shows the config differences between newconfig and Kconfig. In theory, all Kconfig configs should be equal to their newconfig pendant. In practice it's better to come close but stay clean. --> Please help porting all boards from newconfig to Kconfig <-- git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5082 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
This commit is contained in:
parent
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@ -21,3 +21,13 @@
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config CPU_AMD_GX1
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config CPU_AMD_GX1
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bool
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bool
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config DCACHE_RAM_BASE
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hex
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default 0xc0000
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depends on CPU_AMD_GX1
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config DCACHE_RAM_SIZE
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hex
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default 0x01000
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depends on CPU_AMD_GX1
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@ -1,2 +1,32 @@
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##
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## This file is part of the coreboot project.
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##
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## Copyright (C) 2010 coresystems GmbH
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##
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## This program is free software; you can redistribute it and/or modify
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## it under the terms of the GNU General Public License as published by
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## the Free Software Foundation; version 2 of the License.
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##
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## This program is distributed in the hope that it will be useful,
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## but WITHOUT ANY WARRANTY; without even the implied warranty of
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## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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## GNU General Public License for more details.
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##
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## You should have received a copy of the GNU General Public License
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## along with this program; if not, write to the Free Software
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## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
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##
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config CPU_AMD_GX2
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config CPU_AMD_GX2
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bool
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bool
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config DCACHE_RAM_BASE
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hex
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default 0xc0000
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depends on CPU_AMD_GX2
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config DCACHE_RAM_SIZE
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hex
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default 0x01000
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depends on CPU_AMD_GX2
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@ -1,3 +1,13 @@
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config CPU_AMD_LX
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config CPU_AMD_LX
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bool
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bool
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on CPU_AMD_LX
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on CPU_AMD_LX
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@ -21,3 +21,13 @@
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config CPU_INTEL_SLOT_2
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config CPU_INTEL_SLOT_2
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bool
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bool
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config DCACHE_RAM_BASE
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hex
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default 0xc0000
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depends on CPU_INTEL_SLOT_2
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config DCACHE_RAM_SIZE
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hex
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default 0x01000
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depends on CPU_INTEL_SLOT2
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@ -32,16 +32,6 @@ config IRQ_SLOT_COUNT
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default 4
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default 4
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depends on BOARD_AMD_DB800
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depends on BOARD_AMD_DB800
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_AMD_DB800
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_AMD_DB800
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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default 6
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default 6
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depends on BOARD_AMD_NORWICH
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depends on BOARD_AMD_NORWICH
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_AMD_NORWICH
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_AMD_NORWICH
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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default 3
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default 3
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depends on BOARD_ARTECGROUP_DBE61
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depends on BOARD_ARTECGROUP_DBE61
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_ARTECGROUP_DBE61
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_ARTECGROUP_DBE61
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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default 9
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default 9
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depends on BOARD_DIGITALLOGIC_MSM800SEV
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depends on BOARD_DIGITALLOGIC_MSM800SEV
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_DIGITALLOGIC_MSM800SEV
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_DIGITALLOGIC_MSM800SEV
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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default 9
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default 9
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depends on BOARD_IEI_PCISA_LX_800_R10
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depends on BOARD_IEI_PCISA_LX_800_R10
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_IEI_PCISA_LX_800_R10
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_IEI_PCISA_LX_800_R10
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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default 7
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default 7
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depends on BOARD_LIPPERT_ROADRUNNER_LX
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depends on BOARD_LIPPERT_ROADRUNNER_LX
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_LIPPERT_ROADRUNNER_LX
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_LIPPERT_ROADRUNNER_LX
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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default 7
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default 7
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depends on BOARD_LIPPERT_SPACERUNNER_LX
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depends on BOARD_LIPPERT_SPACERUNNER_LX
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_LIPPERT_SPACERUNNER_LX
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_LIPPERT_SPACERUNNER_LX
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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default 5
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default 5
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depends on BOARD_PCENGINES_ALIX1C
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depends on BOARD_PCENGINES_ALIX1C
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config DCACHE_RAM_BASE
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hex
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default 0xc8000
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depends on BOARD_PCENGINES_ALIX1C
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config DCACHE_RAM_SIZE
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hex
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default 0x8000
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depends on BOARD_PCENGINES_ALIX1C
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config RAMBASE
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config RAMBASE
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hex
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hex
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default 0x4000
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default 0x4000
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sed \
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sed \
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-e "/^CONFIG_CONSOLE_/ d" \
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-e "/^CONFIG_CONSOLE_/ d" \
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-e "/^CONFIG_MAXIMUM_CONSOLE_LOGLEVEL/ d" \
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-e "/^CONFIG_DEFAULT_CONSOLE_LOGLEVEL/ d" \
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-e "/^CONFIG_RESET_/ d" \
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-e "/^CONFIG_RESET_/ d" \
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-e "/^CONFIG_XIP_ROM_/ d" \
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-e "/^CONFIG_XIP_ROM_/ d" \
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-e "/^CONFIG_PRECOMPRESSED_PAYLOAD / d" \
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-e "/^CONFIG_PRECOMPRESSED_PAYLOAD / d" \
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-e "/^CONFIG_STACK_SIZE / d" \
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-e "/^CONFIG_STACK_SIZE / d" \
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-e "/^CONFIG_GDB_STUB / d" \
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-e "/^CONFIG_GDB_STUB / d" \
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-e "/^CONFIG_VIDEO_MB / d" \
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-e "/^CONFIG_VIDEO_MB / d" \
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-e "/^CONFIG_IOAPIC / d" \
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-e "/^CONFIG_HAVE_MOVNTI / d" \
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-e "/^CONFIG_HAVE_MOVNTI / d" \
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-e "/^CONFIG_PCIE_CONFIGSPACE_HOLE / d" \
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-e "/^CONFIG_PCIE_CONFIGSPACE_HOLE / d" \
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$A/old > $A/old.filtered
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$A/old > $A/old.filtered
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