From 04da829a0f4fa997514dc3131251f6f849158131 Mon Sep 17 00:00:00 2001 From: Nick Chen Date: Thu, 17 Dec 2020 14:26:38 +0800 Subject: [PATCH] volteer/variants/eldrid: Enable RTD3 for the NVMe device Enable Runtime D3 for the volteer variants that have GPIO power control of the NVMe device attached to PCIe Root Port 9. Enable the GPIO for power control for variants that do not already have it configured to allow the power to be disabled in D3 state. BUG=b:161270810 TEST=tested on eldrid Signed-off-by: Nick Chen Change-Id: I941c8a9bb3221ad90528c323cd0f267dc77d2af3 Reviewed-on: https://review.coreboot.org/c/coreboot/+/48687 Tested-by: build bot (Jenkins) Reviewed-by: Tim Wawrzynczak --- src/mainboard/google/volteer/variants/eldrid/gpio.c | 2 +- .../google/volteer/variants/eldrid/overridetree.cb | 8 ++++++++ 2 files changed, 9 insertions(+), 1 deletion(-) diff --git a/src/mainboard/google/volteer/variants/eldrid/gpio.c b/src/mainboard/google/volteer/variants/eldrid/gpio.c index e92f6b100b..d2b08bc63e 100644 --- a/src/mainboard/google/volteer/variants/eldrid/gpio.c +++ b/src/mainboard/google/volteer/variants/eldrid/gpio.c @@ -24,7 +24,7 @@ static const struct pad_config override_gpio_table[] = { PAD_CFG_NF(GPP_A23, NONE, DEEP, NF1), /* B2 : VRALERT# ==> EN_PP3300_SSD */ - PAD_CFG_NF(GPP_B2, NONE, DEEP, NF1), + PAD_CFG_GPO(GPP_B2, 1, DEEP), /* B7 : ISH_12C1_SDA ==> ISH_I2C0_SENSOR_SDA */ PAD_CFG_NF(GPP_B7, NONE, DEEP, NF1), /* B8 : ISH_I2C1_SCL ==> ISH_I2C0_SENSOR_SCL */ diff --git a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb index 1b86e0ef6c..08d013e941 100644 --- a/src/mainboard/google/volteer/variants/eldrid/overridetree.cb +++ b/src/mainboard/google/volteer/variants/eldrid/overridetree.cb @@ -175,6 +175,14 @@ chip soc/intel/tigerlake device pnp 0c09.0 on end end end + device ref pcie_rp9 on + chip soc/intel/common/block/pcie/rtd3 + register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_B2)" + register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_A11)" + register "srcclk_pin" = "0" + device generic 0 on end + end + end device ref hda on chip drivers/generic/max98357a register "hid" = ""MX98357A""