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siemens/mc_apl3: Set Full Reset Bit into Reset Control Register 

This mainboard provides customer hardware reset button. A feature of
this button is that it holds the APL in reset state as long as the reset
button is pressed. After releasing the reset button the APL should
restart again without the need for a power cycle. When Bit 3 in Reset
Control Register (I/O port CF9h) is set to 1 and then the reset button
is pressed the PCH will drive SLP_S3 active (low).

Change-Id: Ib842f15b6ba14851d7f9b1b97c83389adc61f50b
Signed-off-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Reviewed-on: https://review.coreboot.org/29530
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>
This commit is contained in:
Mario Scheithauer 2018-11-07 12:58:28 +01:00 committed by Werner Zeh
parent d985cdc763
commit 04ea73ee78
1 changed files with 8 additions and 0 deletions
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8
src/mainboard/siemens/mc_apl1/variants/mc_apl3/mainboard.c
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@ -14,6 +14,7 @@
*/ */
#include <bootstate.h> #include <bootstate.h>
#include <cf9_reset.h>
#include <console/console.h> #include <console/console.h>
#include <device/pci_def.h> #include <device/pci_def.h>
#include <device/pci_ids.h> #include <device/pci_ids.h>
@ -62,6 +63,13 @@ void variant_mainboard_final(void)
cmd |= PCI_COMMAND_MASTER; cmd |= PCI_COMMAND_MASTER;
pci_write_config16(dev, PCI_COMMAND, cmd); pci_write_config16(dev, PCI_COMMAND, cmd);
} }
/* Set Full Reset Bit in Reset Control Register (I/O port CF9h).
* When Bit 3 is set to 1 and then the reset button is pressed the PCH
* will drive SLP_S3 active (low). SLP_S3 is then used on the mainboard
* to generate the right reset timing.
*/
outb(FULL_RST, RST_CNT);
} }
static void wait_for_legacy_dev(void *unused) static void wait_for_legacy_dev(void *unused)