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nb/intel/gm45/raminit: Use read32p() 

Built roda/rk9 with BUILD_TIMELESS=1 and the resulting coreboot.rom
remains identical.

Change-Id: Ib1e7144eebf8148c4eb5cc0e7bc03ae3d7281092
Signed-off-by: Elyes Haouas <ehaouas@noos.fr>
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/77971
Reviewed-by: Felix Singer <service+coreboot-gerrit@felixsinger.de>
Reviewed-by: Felix Held <felix-coreboot@felixheld.de>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
This commit is contained in:
Elyes Haouas 2023-09-17 09:49:43 +02:00 committed by Felix Held
parent 0d50536a50
commit 0509009f79
1 changed files with 1 additions and 1 deletions
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2
src/northbridge/intel/gm45/raminit.c
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@ -1965,7 +1965,7 @@ static void jedec_init_ddr2(const timings_t *const timings,
jedec_command(rankaddr, DCC_CMD_ABP, 0); jedec_command(rankaddr, DCC_CMD_ABP, 0);
jedec_command(rankaddr, DCC_CMD_CBR, 0); jedec_command(rankaddr, DCC_CMD_CBR, 0);
udelay(1); udelay(1);
read32((void *)(rankaddr)); read32p(rankaddr);
jedec_command(rankaddr, DCC_SET_MREG, WR | CAS | BTinterleaved | BL8); jedec_command(rankaddr, DCC_SET_MREG, WR | CAS | BTinterleaved | BL8);
jedec_command(rankaddr, DCC_SET_EREGx(1), OCDdefault | ODT_150OHMS); jedec_command(rankaddr, DCC_SET_EREGx(1), OCDdefault | ODT_150OHMS);