soc/amd/stoneyridge: Add southbridge definitions
* Add definitions to iomap.h for AMD ACPI MMIO base addresses. * Add FCH AOAC registers for enabling FCH devices. * From: BIOS and Kernel Developer's Guide (BKDG) for AMD Family 15h, Models 70h-7Fh Processors Rev 3.04 BUG=b:69220826 BRANCH=master TEST=abuild, build Gardenia, build and boot Grunt Change-Id: I45c1d1d7edc864000282c7ca4e2b8f2a14ea9eac Signed-off-by: Garrett Kirkendall <garrett.kirkendall@amd.corp-partner.google.com> Reviewed-on: https://review.coreboot.org/24998 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Martin Roth <martinroth@google.com> Reviewed-by: Richard Spiegel <richard.spiegel@silverbackltd.com>
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@ -37,7 +37,11 @@
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#define APU_SMI_BASE 0xfed80200
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#define PM_MMIO_BASE 0xfed80300
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#define BIOSRAM_MMIO_BASE 0xfed80500
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#define IOMUX_MMIO_BASE 0xfed80d00
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#define MISC_MMIO_BASE 0xfed80e00
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#define XHCI_ACPI_PM_MMIO_BASE 0xfed81c00
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#define AOAC_MMIO_BASE 0xfed81e00
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#define APU_UART0_BASE 0xfedc6000
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#define APU_UART1_BASE 0xfedc8000
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@ -289,6 +289,46 @@
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#define GPIO_TABLE_BOOTBLOCK 0
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#endif
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/* FCH AOAC Registers 0xfed81e00 */
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#define FCH_AOAC_D3_CONTROL_CLK_GEN 0x40
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#define FCH_AOAC_D3_CONTROL_I2C0 0x4A
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#define FCH_AOAC_D3_CONTROL_I2C1 0x4C
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#define FCH_AOAC_D3_CONTROL_I2C2 0x4E
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#define FCH_AOAC_D3_CONTROL_I2C3 0x50
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#define FCH_AOAC_D3_CONTROL_UART0 0x56
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#define FCH_AOAC_D3_CONTROL_UART1 0x58
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#define FCH_AOAC_D3_CONTROL_AMBA 0x62
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#define FCH_AOAC_D3_CONTROL_USB2 0x64
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#define FCH_AOAC_D3_CONTROL_USB3 0x6E
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/* Bit definitions for all FCH_AOAC_D3_CONTROL_* Registers */
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#define FCH_AOAC_TARGET_DEVICE_STATE (BIT(0) + BIT(1))
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#define FCH_AOAC_DEVICE_STATE BIT(2)
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#define FCH_AOAC_PWR_ON_DEV BIT(3)
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#define FCH_AOAC_SW_PWR_ON_RSTB BIT(4)
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#define FCH_AOAC_SW_REF_CLK_OK BIT(5)
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#define FCH_AOAC_SW_RST_B BIT(6)
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#define FCH_AOAC_IS_SW_CONTROL BIT(7)
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#define FCH_AOAC_D3_STATE_CLK_GEN 0x41
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#define FCH_AOAC_D3_STATE_I2C0 0x4B
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#define FCH_AOAC_D3_STATE_I2C1 0x4D
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#define FCH_AOAC_D3_STATE_I2C2 0x4F
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#define FCH_AOAC_D3_STATE_I2C3 0x51
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#define FCH_AOAC_D3_STATE_UART0 0x57
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#define FCH_AOAC_D3_STATE_UART1 0x59
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#define FCH_AOAC_D3_STATE_AMBA 0x63
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#define FCH_AOAC_D3_STATE_USB2 0x65
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#define FCH_AOAC_D3_STATE_USB3 0x6F
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/* Bit definitions for all FCH_AOAC_D3_STATE_* Registers */
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#define FCH_AOAC_PWR_RST_STATE BIT(0)
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#define FCH_AOAC_RST_CLK_OK_STATE BIT(1)
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#define FCH_AOAC_RST_B_STATE BIT(2)
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#define FCH_AOAC_DEV_OFF_GATING_STATE BIT(3)
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#define FCH_AOAC_D3COLD BIT(4)
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#define FCH_AOAC_CLK_OK_STATE BIT(5)
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#define FCH_AOAC_STAT0 BIT(6)
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#define FCH_AOAC_STAT1 BIT(7)
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struct soc_amd_stoneyridge_gpio {
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uint8_t gpio;
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uint8_t function;
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