From 05172526beeea33bb21d8b190a585992ded6f10c Mon Sep 17 00:00:00 2001 From: MAULIK V VAGHELA Date: Thu, 12 Aug 2021 23:08:51 +0530 Subject: [PATCH] mb/*/{tglrvp,volteer,deltaur}: Remove hardcoding of BSP APIC ID MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit coreboot always assumes that BSP APIC ID will be 0 and core enumeration logic will look for lapic id from the mainboard. As per Intel 64 and IA-32 Architectures Software Developer’s Manual Volume 3: 8.4.1 BSP and AP Processors, this assumption might not hold true and we may have any other core as BSP. To handle this, we need to remove hardcoding of APIC ID 0 from mainboard. BUG=None BRANCH=None TEST=Check if there is no functional impact on the board. Change-Id: I175ae26f934f08e125bea7cc3195bdb5792c2360 Signed-off-by: MAULIK V VAGHELA Reviewed-on: https://review.coreboot.org/c/coreboot/+/56954 Reviewed-by: Subrata Banik Tested-by: build bot (Jenkins) --- src/mainboard/google/deltaur/variants/baseboard/devicetree.cb | 4 +--- src/mainboard/google/volteer/variants/baseboard/devicetree.cb | 4 +--- src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 4 +--- src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 4 +--- 4 files changed, 4 insertions(+), 12 deletions(-) diff --git a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb index 4a0c49f2aa..27f3211034 100644 --- a/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/deltaur/variants/baseboard/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb index e2a84f8138..abb8bdc34d 100644 --- a/src/mainboard/google/volteer/variants/baseboard/devicetree.cb +++ b/src/mainboard/google/volteer/variants/baseboard/devicetree.cb @@ -79,9 +79,7 @@ end chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4e3d2e798e..66eb027914 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index 7f7e16b10a..c4bbdda615 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -1,8 +1,6 @@ chip soc/intel/tigerlake - device cpu_cluster 0 on - device lapic 0 on end - end + device cpu_cluster 0 on end # GPE configuration # Note that GPE events called out in ASL code rely on this