From 052fb7c45136263ed194c24fd4d04488a2608fd3 Mon Sep 17 00:00:00 2001 From: Jeremy Compostella Date: Fri, 18 Aug 2023 14:25:22 -0700 Subject: [PATCH] x86: Add pre-memory stages CBFS cache scratchpad support Having a CBFS cache scratchpad offers a generic way to decompress CBFS files through the cbfs_map() function without having to reserve a per-file specific memory region. This commit introduces the x86 `PRERAM_CBFS_CACHE_SIZE' Kconfig to set the pre-memory stages CBFS cache size. A cache size of zero disables the CBFS cache feature. The default value is 16 KB which seems a reasonable minimal value enough to satisfy basic needs such as the decompression of a small configuration file. This setting can be adjusted depending on the platform needs and capabilities. We have set this size to zero for all the platforms without enough space in Cache-As-RAM to accommodate the default size. TEST=Decompression of vbt.bin in romstage on rex using cbfs_map() Change-Id: Iee493f9947fddcc57576f04c3d6a2d58c7368e09 Signed-off-by: Jeremy Compostella Reviewed-on: https://review.coreboot.org/c/coreboot/+/77290 Tested-by: build bot (Jenkins) Reviewed-by: Arthur Heymans --- src/arch/x86/Kconfig | 7 +++++++ src/arch/x86/car.ld | 3 +++ src/cpu/intel/slot_1/Kconfig | 3 +++ src/cpu/intel/socket_441/Kconfig | 3 +++ src/cpu/intel/socket_BGA956/Kconfig | 3 +++ src/cpu/intel/socket_FCBGA559/Kconfig | 3 +++ src/cpu/intel/socket_LGA775/Kconfig | 3 +++ src/cpu/intel/socket_m/Kconfig | 3 +++ src/cpu/intel/socket_mPGA604/Kconfig | 3 +++ src/northbridge/intel/sandybridge/Kconfig | 3 +++ src/soc/amd/stoneyridge/Kconfig | 3 +++ src/soc/intel/baytrail/Kconfig | 3 +++ src/soc/intel/braswell/Kconfig | 3 +++ 13 files changed, 43 insertions(+) diff --git a/src/arch/x86/Kconfig b/src/arch/x86/Kconfig index c97fecb3e4..b0e479b1c4 100644 --- a/src/arch/x86/Kconfig +++ b/src/arch/x86/Kconfig @@ -153,6 +153,13 @@ config CBFS_MCACHE_SIZE Increase this value if you see CBFS mcache overflow warnings. Do NOT change this value for vboot RW updates! +config PRERAM_CBFS_CACHE_SIZE + hex + default 0x4000 + help + Define the size of the Pre-RAM stages CBFS cache. A size of + zero disables the CBFS cache feature in pre-memory stages. + config PC80_SYSTEM bool default y if ARCH_X86 diff --git a/src/arch/x86/car.ld b/src/arch/x86/car.ld index 14fdba6331..2ad1ca2cd8 100644 --- a/src/arch/x86/car.ld +++ b/src/arch/x86/car.ld @@ -51,6 +51,9 @@ FMAP_CACHE(., FMAP_SIZE) #endif + . = ALIGN(CONFIG_CBFS_CACHE_ALIGN); + CBFS_CACHE(., CONFIG_PRERAM_CBFS_CACHE_SIZE) + /* Reserve sizeof(struct ehci_dbg_info). */ REGION(car_ehci_dbg_info, ., 80, 1) diff --git a/src/cpu/intel/slot_1/Kconfig b/src/cpu/intel/slot_1/Kconfig index 4ba8747012..fffca39585 100644 --- a/src/cpu/intel/slot_1/Kconfig +++ b/src/cpu/intel/slot_1/Kconfig @@ -24,6 +24,9 @@ config DCACHE_RAM_SIZE hex default 0x02000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x1000 diff --git a/src/cpu/intel/socket_441/Kconfig b/src/cpu/intel/socket_441/Kconfig index 1a549ac328..381b72b3a8 100644 --- a/src/cpu/intel/socket_441/Kconfig +++ b/src/cpu/intel/socket_441/Kconfig @@ -13,6 +13,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_BGA956/Kconfig b/src/cpu/intel/socket_BGA956/Kconfig index 7c42722e82..9197faae9e 100644 --- a/src/cpu/intel/socket_BGA956/Kconfig +++ b/src/cpu/intel/socket_BGA956/Kconfig @@ -12,6 +12,9 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_FCBGA559/Kconfig b/src/cpu/intel/socket_FCBGA559/Kconfig index 223f80d228..95099c58c6 100644 --- a/src/cpu/intel/socket_FCBGA559/Kconfig +++ b/src/cpu/intel/socket_FCBGA559/Kconfig @@ -15,6 +15,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_LGA775/Kconfig b/src/cpu/intel/socket_LGA775/Kconfig index 63d6250c62..870fd78ea0 100644 --- a/src/cpu/intel/socket_LGA775/Kconfig +++ b/src/cpu/intel/socket_LGA775/Kconfig @@ -12,6 +12,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 # 32 kB +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_m/Kconfig b/src/cpu/intel/socket_m/Kconfig index 2e653e97c1..2e6d432718 100644 --- a/src/cpu/intel/socket_m/Kconfig +++ b/src/cpu/intel/socket_m/Kconfig @@ -13,6 +13,9 @@ config DCACHE_RAM_SIZE hex default 0x8000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/cpu/intel/socket_mPGA604/Kconfig b/src/cpu/intel/socket_mPGA604/Kconfig index 8f28670a1d..92a0b43e0f 100644 --- a/src/cpu/intel/socket_mPGA604/Kconfig +++ b/src/cpu/intel/socket_mPGA604/Kconfig @@ -17,6 +17,9 @@ config DCACHE_RAM_SIZE hex default 0x4000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x2000 diff --git a/src/northbridge/intel/sandybridge/Kconfig b/src/northbridge/intel/sandybridge/Kconfig index b7738a2080..34a0939455 100644 --- a/src/northbridge/intel/sandybridge/Kconfig +++ b/src/northbridge/intel/sandybridge/Kconfig @@ -172,4 +172,7 @@ config FIXED_DMIBAR_MMIO_BASE config FIXED_EPBAR_MMIO_BASE default 0xfed19000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + endif diff --git a/src/soc/amd/stoneyridge/Kconfig b/src/soc/amd/stoneyridge/Kconfig index 6ff135e6a8..bd55b71f0f 100644 --- a/src/soc/amd/stoneyridge/Kconfig +++ b/src/soc/amd/stoneyridge/Kconfig @@ -103,6 +103,9 @@ config DCACHE_RAM_SIZE hex default 0x10000 +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_BSP_STACK_SIZE hex default 0x4000 diff --git a/src/soc/intel/baytrail/Kconfig b/src/soc/intel/baytrail/Kconfig index 13fd201f9f..dbadbf1105 100644 --- a/src/soc/intel/baytrail/Kconfig +++ b/src/soc/intel/baytrail/Kconfig @@ -110,6 +110,9 @@ config DCACHE_RAM_SIZE and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config DCACHE_RAM_MRC_VAR_SIZE hex default 0x8000 diff --git a/src/soc/intel/braswell/Kconfig b/src/soc/intel/braswell/Kconfig index ba6450bec7..5aeb9e56ec 100644 --- a/src/soc/intel/braswell/Kconfig +++ b/src/soc/intel/braswell/Kconfig @@ -97,6 +97,9 @@ config DCACHE_RAM_SIZE and/or romstage. Note DCACHE_RAM_SIZE and DCACHE_RAM_MRC_VAR_SIZE must add up to a power of 2. +config PRERAM_CBFS_CACHE_SIZE + default 0x0 + config ENABLE_BUILTIN_COM1 bool "Enable builtin COM1 Serial Port" default n