From 053a45bcdb3ccf8a686b35c97e8404c386f65d58 Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Ky=C3=B6sti=20M=C3=A4lkki?= Date: Wed, 28 Jun 2023 06:16:36 +0300 Subject: [PATCH] cpu/x86/lapic: Fix X2APIC_ONLY regression MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Some ancient CPUs may have had LAPIC disabled at power-up, so semantically enable_lapic() should always come before attempting to access the register banks. With X2APIC_ONLY option it is necessary to ensure enable_lapic() is called prior to any other lapic register space accesses, since the XAPIC mode MMIO accessors are optimised away build-time and CPU's do not yet initialise for X2APIC mode at reset. Change-Id: I96eaa5c43108c802375e184e0c68b5091ca0198f Signed-off-by: Kyösti Mälkki Reviewed-on: https://review.coreboot.org/c/coreboot/+/76195 Reviewed-by: Arthur Heymans Tested-by: build bot (Jenkins) Reviewed-by: Elyes Haouas Reviewed-by: Felix Held --- src/cpu/x86/mtrr/mtrr.c | 2 ++ 1 file changed, 2 insertions(+) diff --git a/src/cpu/x86/mtrr/mtrr.c b/src/cpu/x86/mtrr/mtrr.c index a3a89fe0cd..f467145074 100644 --- a/src/cpu/x86/mtrr/mtrr.c +++ b/src/cpu/x86/mtrr/mtrr.c @@ -806,6 +806,8 @@ static void _x86_setup_mtrrs(unsigned int above4gb) { int address_size; + enable_lapic(); + x86_setup_fixed_mtrrs(); address_size = cpu_phys_address_size(); printk(BIOS_DEBUG, "apic_id 0x%x setup mtrr for CPU physical address size: %d bits\n",