mb/google/volteer/var/voxel: Add Raydium touchscreen support
Update gpio GPP_E7 and enable the Raydium TS support BUG=b:157402209,b:162632701,b:162636271 BRANCH=master TEST= 1. emerge-volteer coreboot chromeos-bootimage 2. boot up on voxel DUT and make sure the raydium TS can work. Signed-off-by: David Wu <david_wu@quanta.corp-partner.google.com> Change-Id: I377aded4982ece71f4dabb58f307f68c713edcd2 Reviewed-on: https://review.coreboot.org/c/coreboot/+/44055 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: YH Lin <yueherngl@google.com> Reviewed-by: Paul Fagerburg <pfagerburg@chromium.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: Caveh Jalali <caveh@chromium.org> Reviewed-by: Sheng-Liang Pan <sheng-liang.pan@quanta.corp-partner.google.com>
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@ -117,7 +117,7 @@ static const struct pad_config override_gpio_table[] = {
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/* E3 : CPU_GP0 ==> USI_REPORT_EN */
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PAD_CFG_GPO(GPP_E3, 1, DEEP),
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/* E7 : CPU_GP1 ==> USI_INT */
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PAD_CFG_GPI(GPP_E7, NONE, DEEP),
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PAD_CFG_GPI_APIC(GPP_E7, NONE, PLTRST, LEVEL, NONE),
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/* E8 : SPI1_CS1# ==> SLP_S0IX */
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PAD_CFG_GPO(GPP_E8, 0, DEEP),
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/* E10 : SPI1_CS# ==> NC(TP94508) */
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@ -63,6 +63,20 @@ chip soc/intel/tigerlake
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register "hid_desc_reg_offset" = "0x01"
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device i2c 10 on end
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end
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chip drivers/i2c/generic
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register "hid" = ""RAYD0001""
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register "desc" = ""Raydium Touchscreen""
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register "irq" = "ACPI_IRQ_EDGE_LOW(GPP_E7_IRQ)"
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register "probed" = "1"
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register "reset_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_LOW(GPP_C10)"
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register "reset_delay_ms" = "1"
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register "reset_off_delay_ms" = "2"
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register "enable_gpio" = "ACPI_GPIO_OUTPUT_ACTIVE_HIGH(GPP_A8)"
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register "enable_delay_ms" = "10"
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register "enable_off_delay_ms" = "1"
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register "has_power_resource" = "1"
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device i2c 39 on end
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end
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end # I2C1 0xA0E9
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device pci 15.2 on
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chip drivers/i2c/sx9310
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