AMD Merlin Falcon: Add northbridge files for new AMD processor

Tested on Bettong. Windows 7, Windows 8.1 and Ubuntu 14.04 can boot.

Change-Id: Ifcbfa0eab74875638a40e74ba2a3bb7c4fb02761
Signed-off-by: WANG Siyuan <wangsiyuanbuaa@gmail.com>
Signed-off-by: WANG Siyuan <SiYuan.Wang@amd.com>
Reviewed-on: http://review.coreboot.org/10419
Tested-by: build bot (Jenkins)
Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

src/include/device/pci_ids.h

@@ -289,6 +289,7 @@
 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_HT	0x141A
 #define PCI_DEVICE_ID_AMD_16H_MODEL_000F_NB_HT	0x1536
 #define PCI_DEVICE_ID_AMD_16H_MODEL_003F_NB_HT  0x1566
+#define PCI_DEVICE_ID_AMD_15H_MODEL_006F_NB_HT	0x1570
 #define PCI_DEVICE_ID_AMD_10H_NB_HT		0x1200
 #define PCI_DEVICE_ID_AMD_15H_NB_IOMMU		0x1419
 #define PCI_DEVICE_ID_AMD_15H_MODEL_303F_NB_IOMMU	0x1423

src/northbridge/amd/pi/00660F01/Kconfig

@@ -0,0 +1,53 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2015 Advanced Micro Devices, Inc.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc.
+##
+config NORTHBRIDGE_AMD_PI_00660F01
+	bool
+	select MMCONF_SUPPORT
+	select PER_DEVICE_ACPI_TABLES
+
+if NORTHBRIDGE_AMD_PI_00660F01
+
+config HW_MEM_HOLE_SIZEK
+	hex
+	default 0x100000
+
+config HW_MEM_HOLE_SIZE_AUTO_INC
+	bool
+	default n
+
+config MMCONF_BASE_ADDRESS
+	hex
+	default 0xF8000000
+
+config MMCONF_BUS_NUMBER
+	int
+	default 64
+
+config VGA_BIOS_ID
+	string
+	default "1002,9870"
+	help
+	  The default VGA BIOS PCI vendor/device ID should be set to the
+	  result of the map_oprom_vendev() function in northbridge.c.
+
+config VGA_BIOS_FILE
+	string
+	default "3rdparty/blobs/northbridge/amd/00660F01/VBIOS.bin"
+
+endif

src/northbridge/amd/pi/00660F01/Makefile.inc

@@ -0,0 +1,22 @@
+#
+# This file is part of the coreboot project.
+#
+# Copyright (C) 2015 Advanced Micro Devices, Inc.
+#
+# This program is free software; you can redistribute it and/or modify
+# it under the terms of the GNU General Public License as published by
+# the Free Software Foundation; version 2 of the License.
+#
+# This program is distributed in the hope that it will be useful,
+# but WITHOUT ANY WARRANTY; without even the implied warranty of
+# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+# GNU General Public License for more details.
+#
+# You should have received a copy of the GNU General Public License
+# along with this program; if not, write to the Free Software
+# Foundation, Inc.
+#
+
+romstage-y += dimmSpd.c
+
+ramstage-y += northbridge.c

src/northbridge/amd/pi/00660F01/acpi/northbridge.asl

@@ -0,0 +1,100 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+/* Note: Only need HID on Primary Bus */
+External (TOM1)
+External (TOM2)
+Name(_HID, EISAID("PNP0A08"))	/* PCI Express Root Bridge */
+Name(_CID, EISAID("PNP0A03"))	/* PCI Root Bridge */
+Name(_ADR, 0x00180000)	/* Dev# = BSP Dev#, Func# = 0 */
+
+/* Describe the Northbridge devices */
+
+Method(_BBN, 0, NotSerialized)	/* Bus number = 0 */
+{
+	Return(Zero)
+}
+
+Method(_STA, 0, NotSerialized)
+{
+	Return(0x0B)	/* Status is visible */
+}
+
+Method(_PRT,0, NotSerialized)
+{
+	If(PMOD)
+	{
+		Return(APR0)	/* APIC mode */
+	}
+	Return (PR0)		/* PIC Mode */
+}
+
+Device(AMRT) {
+	Name(_ADR, 0x00000000)
+} /* end AMRT */
+
+/* Gpp 0 */
+Device(PBR4) {
+	Name(_ADR, 0x00020001)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS4) }	/* APIC mode */
+		Return (PS4)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR4 */
+
+/* Gpp 1 */
+Device(PBR5) {
+	Name(_ADR, 0x00020002)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS5) }	/* APIC mode */
+		Return (PS5)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR5 */
+
+/* Gpp 2 */
+Device(PBR6) {
+	Name(_ADR, 0x00020003)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS6) }	/* APIC mode */
+		Return (PS6)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR6 */
+
+/* Gpp 3 */
+Device(PBR7) {
+	Name(_ADR, 0x00020004)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS7) }	/* APIC mode */
+		Return (PS7)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR7 */
+
+/* Gpp 4 */
+Device(PBR8) {
+	Name(_ADR, 0x00020005)
+	Name(_PRW, Package() {0x18, 4})
+	Method(_PRT,0) {
+		If(PMOD){ Return(APS8) }	/* APIC mode */
+		Return (PS8)			/* PIC Mode */
+	} /* end _PRT */
+} /* end PBR8 */

src/northbridge/amd/pi/00660F01/chip.h

@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2013 Sage Electronic Engineering, LLC
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef _PI_FAM15CZ_CHIP_H_
+#define _PI_FAM15CZ_CHIP_H_
+
+struct northbridge_amd_pi_00660F01_config
+{
+	u8 spdAddrLookup[2][2][4];
+};
+
+#endif

src/northbridge/amd/pi/00660F01/dimmSpd.c

@@ -0,0 +1,53 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#include <device/pci_def.h>
+#include <device/device.h>
+#include <stdlib.h>
+
+/* warning: Porting.h includes an open #pragma pack(1) */
+#include "Porting.h"
+#include "AGESA.h"
+#include "amdlib.h"
+#include "chip.h"
+#include "northbridge/amd/pi/dimmSpd.h"
+
+AGESA_STATUS AmdMemoryReadSPD (UINT32 unused1, UINT32 unused2, AGESA_READ_SPD_PARAMS *info)
+{
+	int spdAddress;
+	ROMSTAGE_CONST struct device *dev = dev_find_slot(0, PCI_DEVFN(0x18, 2));
+	ROMSTAGE_CONST struct northbridge_amd_pi_00660F01_config *config = dev->chip_info;
+
+	if ((dev == 0) || (config == 0))
+		return AGESA_ERROR;
+	if (info->SocketId >= ARRAY_SIZE(config->spdAddrLookup))
+		return AGESA_ERROR;
+	if (info->MemChannelId >= ARRAY_SIZE(config->spdAddrLookup[0]))
+		return AGESA_ERROR;
+	if (info->DimmId >= ARRAY_SIZE(config->spdAddrLookup[0][0]))
+		return AGESA_ERROR;
+	spdAddress = config->spdAddrLookup
+		[info->SocketId] [info->MemChannelId] [info->DimmId];
+	if (spdAddress == 0)
+		return AGESA_ERROR;
+	int err = hudson_readSpd(spdAddress, (void *) info->Buffer, 128);
+	if (err)
+		return AGESA_ERROR;
+	return AGESA_SUCCESS;
+}

src/northbridge/amd/pi/00660F01/northbridge.h

@@ -0,0 +1,26 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2015 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc.
+ */
+
+#ifndef NORTHBRIDGE_AMD_AGESA_FAM16H_H
+#define NORTHBRIDGE_AMD_AGESA_FAM16H_H
+
+static struct device_operations pci_domain_ops;
+static struct device_operations cpu_bus_ops;
+
+#endif /* NORTHBRIDGE_AMD_AGESA_FAM16H_H */

src/northbridge/amd/pi/BiosCallOuts.h

@@ -24,20 +24,10 @@
 #include "Porting.h"
 #include "AGESA.h"
 
-#if CONFIG_NORTHBRIDGE_AMD_PI_00630F01 || CONFIG_NORTHBRIDGE_AMD_PI_00730F01
-
 #define BIOS_HEAP_START_ADDRESS 	0x010000000
 #define BIOS_HEAP_SIZE			0x30000
 #define BSP_STACK_BASE_ADDR		0x30000
 
-#else
-
-#define BIOS_HEAP_START_ADDRESS		0x10000 /* HEAP during cold boot */
-#define BIOS_HEAP_SIZE			0x20000
-#define BSP_STACK_BASE_ADDR		0x30000
-
-#endif
-
 typedef struct _BIOS_HEAP_MANAGER {
 	UINT32 StartOfAllocatedNodes;
 	UINT32 StartOfFreedNodes;

src/northbridge/amd/pi/Kconfig

@@ -34,5 +34,6 @@ config S3_VGA_ROM_RUN
 
 source src/northbridge/amd/pi/00630F01/Kconfig
 source src/northbridge/amd/pi/00730F01/Kconfig
+source src/northbridge/amd/pi/00660F01/Kconfig
 
 endif # NORTHBRIDGE_AMD_PI

src/northbridge/amd/pi/Makefile.inc

@@ -21,6 +21,7 @@ ifeq ($(CONFIG_NORTHBRIDGE_AMD_PI),y)
 
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) += 00630F01
 subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00730F01) += 00730F01
+subdirs-$(CONFIG_NORTHBRIDGE_AMD_PI_00660F01) += 00660F01
 
 romstage-y += agesawrapper.c
 romstage-y += def_callouts.c

src/northbridge/amd/pi/agesawrapper.c

@@ -305,8 +305,10 @@ AGESA_STATUS agesawrapper_amdinitlate(void)
 
 	DmiTable    = AmdLateParams->DmiTable;
 	AcpiPstate  = AmdLateParams->AcpiPState;
+#if IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00630F01) || IS_ENABLED(CONFIG_NORTHBRIDGE_AMD_PI_00730F01)
 	AcpiSrat    = AmdLateParams->AcpiSrat;
 	AcpiSlit    = AmdLateParams->AcpiSlit;
+#endif
 
 	AcpiWheaMce = AmdLateParams->AcpiWheaMce;
 	AcpiWheaCmc = AmdLateParams->AcpiWheaCmc;